HD6413003RVF RENESAS [Renesas Technology Corp], HD6413003RVF Datasheet - Page 559

no-image

HD6413003RVF

Manufacturer Part Number
HD6413003RVF
Description
microcontroller (MCU)
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
18.3.2 Refresh Controller Bus Timing
Refresh controller bus timing is shown as follows:
Note: * Stipulation from earliest CS3 and RD negate timing.
ø
A
AS
CS3 (RAS)
RD (CAS)
HWR (UW),
LWR (LW),
(read)
HWR (UW),
LWR (LW),
(write)
RFSH
D
(read)
D
(write)
9
15
15
DRAM bus timing
Figures 18-7 to 18-12 show the DRAM bus timing in each operating mode.
PSRAM bus timing
Figures 18-13 and 18-14 show the pseudo-static RAM bus timing in each operating mode.
to A
to D
to D
1
0
0
Figure 18-7 DRAM Bus Timing (Read/Write): Three-State Access
t
t
AD
RAD1
t
AS1
T
1
t
RAH
t
ASD
t
t
AD
WDS3
t
RAC
2WE Mode —
t
AS1
T
2
t
t
AA
ASD
541
t
CAC
t
t
RDS
CAS
T
3
t
RAD3
t
t
SD
SD
t
WDH
t
t
RDH*
t
CRP
RP

Related parts for HD6413003RVF