HD6413003RVF RENESAS [Renesas Technology Corp], HD6413003RVF Datasheet - Page 379
HD6413003RVF
Manufacturer Part Number
HD6413003RVF
Description
microcontroller (MCU)
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6413003RVF.pdf
(715 pages)
- Current page: 379 of 715
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Timing of Disabling of ITU Output by External Trigger: If the XTGD bit is cleared to 0 in
TOCR in reset-synchronized PWM mode or complementary PWM mode, when an input capture
A signal occurs in channel 1, the master enable bits are cleared to 0 in TOER, disabling ITU
output. Figure 10-55 shows the timing.
Timing of Output Inversion by TOCR: The output levels in reset-synchronized PWM mode and
complementary PWM mode can be inverted by inverting the output level select bits (OLS4 and
OLS3) in TOCR. Figure 10-56 shows the timing.
ø
TIOCA1 pin
Input capture
signal
TOER
ITU output
pins
N: Arbitrary setting (H'C1 to H'FF)
Figure 10-56 Timing of Inverting of ITU Output Level by Writing to TOCR (Example)
Figure 10-55 Timing of Disabling of ITU Output by External Trigger (Example)
ø
Address
TOCR
ITU output pin
ITU output
ITU output
N
T
1
TOCR address
361
H'C0
T
2
Generic
input/output
I/O port
T
3
Inverted
ITU output
N
ITU output
H'C0
I/O port
Generic
input/output
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