HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 184
HD64F7050
Manufacturer Part Number
HD64F7050
Description
32-Bit RISC Microcomputer SuperH RISC engine Family/
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD64F7050.pdf
(841 pages)
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Section 9 Direct Memory Access Controller (DMAC)
Rev. 5.00 Jan 06, 2006 page 164 of 818
REJ09B0273-0500
2nd bus cycle
3rd bus cycle
4th bus cycle
The value in the temporary buffer is taken as the address, and data is read from the
transfer source module to the data buffer.
The SAR value is taken as the address, memory data is read, and the value is stored in the
temporary buffer. Since the value read at this time is used as the address, it must be 32 bits.
The DAR3 value is taken as the address, and the value in the data buffer is written to the
transfer destination module.
Note:
Figure 9.9 Dual Address Mode and Indirect Address Operation
Memory, transfer source, and transfer destination modules are shown here.
In practice, connection can be made anywhere there is address space.
Temporary
Temporary
Temporary
DMAC
DMAC
buffer
buffer
buffer
buffer
DAR3
DAR3
SAR3
SAR3
Data
Data
DMAC
buffer
buffer
DAR3
SAR3
Data
Transfer destination
Transfer destination
Transfer destination
Transfer source
Transfer source
Transfer source
Memory
Memory
Memory
module
module
module
module
module
module
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