HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 49

• Manufacturer Part Number: HD64F7050
• Description: 32-Bit RISC Microcomputer SuperH RISC engine Family/
• Manufacturer: RENESAS [Renesas Technology Corp]

2.3.2
Table 2.8 describes addressing modes and effective address calculation.
Table 2.8
Addressing
Mode
Direct register
addressing
Indirect register
addressing
Post-increment
indirect register
addressing
Pre-decrement
indirect register
addressing
Addressing Modes
Addressing Modes and Effective Addresses
Instruction
Format
Rn
@Rn
@Rn+
@–Rn
Effective Addresses Calculation
The effective address is register Rn. (The operand
is the contents of register Rn.)
The effective address is the content of register Rn.
The effective address is the content of register Rn.
A constant is added to the content of Rn after the
instruction is executed. 1 is added for a byte
operation, 2 for a word operation, and 4 for a
longword operation.
The effective address is the value obtained by
subtracting a constant from Rn. 1 is subtracted for
a byte operation, 2 for a word operation, and 4 for
a longword operation.
1/2/4
1/2/4
Rn
Rn
Rn
Rn + 1/2/4
Rn – 1/2/4
+
–
Rev. 5.00 Jan 06, 2006 page 29 of 818
Rn – 1/2/4
Rn
Rn
REJ09B0273-0500
Section 2 CPU
Equation
—
Rn
Rn
(After the
instruction
executes)
Byte: Rn + 1
Word: Rn + 2
Longword:
Rn + 4
Byte: Rn – 1
Word: Rn – 2
Longword:
Rn – 4
(Instruction
executed with
Rn after
calculation)
Rn
Rn
Rn
Rn
Rn
Rn