HD64F7050 RENESAS [Renesas Technology Corp], HD64F7050 Datasheet - Page 280
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HD64F7050
Manufacturer Part Number
HD64F7050
Description
32-Bit RISC Microcomputer SuperH RISC engine Family/
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD64F7050.pdf
(841 pages)
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Section 10 Advanced Timer Unit (ATU)
Bit 4—Input Capture/Compare-Match Interrupt Enable (IME4B): Enables or disables
interrupt requests by IMF4B in TSR when IMF4B is set to 1.
Bit 4:
IME4B
0
1
Bit 3—Input Capture/Compare-Match Interrupt Enable (IME4A): Enables or disables
interrupt requests by IMF4A in TSR when IMF4A is set to 1.
Bit 3:
IME4A
0
1
Bit 2—Overflow Interrupt Enable (OVE5): Enables or disables interrupt requests by OVF5 in
TSR when OVF5 is set to 1.
Bit 2:
OVE5
0
1
Bit 1—Input Capture/Compare-Match Interrupt Enable (IME5B): Enables or disables
interrupt requests by IMF5B in TSR when IMF5B is set to 1.
Bit 1:
IME5B
0
1
Rev. 5.00 Jan 06, 2006 page 260 of 818
REJ09B0273-0500
Description
IMI4B interrupt requested by IMF4B is disabled
IMI4B interrupt requested by IMF4B is enabled
Description
IMI4A interrupt requested by IMF4A is disabled
IMI4A interrupt requested by IMF4A is enabled
Description
OVI5 interrupt requested by OVF5 is disabled
OVI5 interrupt requested by OVF5 is enabled
Description
IMI5B interrupt requested by IMF5B is disabled
IMI5B interrupt requested by IMF5B is enabled
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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