SA57026D PHILIPS [NXP Semiconductors], SA57026D Datasheet - Page 5

• Manufacturer Part Number: SA57026D
• Description: 300 mA LDO with ON/OFF control and independent delayed RESET function
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
APPLICATION INFORMATION
Input capacitor
An input capacitor of 1 F is required to eliminate the AC coupling
noise. This capacitor must be located as close as possible to V
GND pin (not more than 1 cm) and returned to a clean analog
ground. Any good quality ceramic, tantalum or film capacitor will
work.
Output capacitor
Phase compensation is made for securing stable operation, even if
the load current varies. For this reason, an output capacitor with
good frequency characteristics is needed. Set it as close to the
circuit as possible, with wires as short as possible.
Tha value of the output capacitance has to be at least 47 F
connected from V
than batteries, supply-noise rejection and transient response can be
improved by increasing the value of the input and output capacitors
and employing passive filtering techniques.
ON/OFF
The regulator is fully enabled when a logic HIGH is applied to this
input. The regulator enters shutdown when a logic LOW is appplied
to this input. During shutdown, regulator output voltage falls to zero,
RESET remains valid and supply current is reduced to 5 A (typ). If
the function is not to be used, the ON/OFF pin should be tied to V
RESET output
The SA57066 has an Active-LOW RESET output. The RESET
output is driven Active-LOW within 30 s typical (when Cd is zero
capacitance). The time delay can be adjusted up to 10 ms typical
(when Cd is 0.1 F) of V
threshold. RESET is maintained Active-HIGH after V
thre reset threshold.
2003 Oct 13
300 mA LDO with ON/OFF control and
independent delayed RESET function
OUT
to GND. When operating from sources other
DET
falling through the reset voltage
1 F
C
RESET
4.7 k
R
DET
Figure 3. Typical application circuit.
V
IN
4
2
rises above
ON/OFF
3
IN
SA57026
or
IN
.
1
5
RESET output delay operation with an external capacitor from
Cd pin to GND
When the supply voltage crosses the release voltage (V
low value to a value higher than the released voltage (V
pin voltage starts to increase (charges up the external capacitor).
While the RESET output remains at LOW state condition until the
Cd pin voltage reaches the threshold operating voltage (V
typical; after that, the RESET output is reversed to HIGH state
condition.
The transmission delay time (t
Cd of an external cpacitor as shown in Equation (1):
(Time is expressed in seconds; capacitance in Farads.)
PCB layout
The component placement around the LDO should be done carefully
to achieve good dynamic line and load response. The input and
noise capacitors should be kept close to the LDO.
The rise in junction temperature depends on how efficiently the heat
is carried away from the junction to ambient. The junction to lead
thermal impedance is a characteristic of the package and fixed. The
thermal impedance between lead to ambient can be reduced by
increasing the copper area on the PCB. Increase the input, output
and ground trace area to reduce the junction-to-ambient impedance.
6
t
PLH
5
7
Cd
V
OUT
10
6
C
0.1 F
C
C
47 F
OUT
SL01530
PLH
) can be set with the capacitance
R
SA57026
DET
DET
Product data
OPL
Eqn. (1)
), the Cd
) from a
) 0.4 V