DM9620 DAVICOM [Davicom Semiconductor, Inc.], DM9620 Datasheet - Page 19

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DM9620

Manufacturer Part Number
DM9620
Description
USB2.0 to 10/100M Fast Ethernet Controller
Manufacturer
DAVICOM [Davicom Semiconductor, Inc.]
Datasheet

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4.5 RX Status Register ( 06H )
4.6 Receive Overflow Counter Register ( 07H )
This register can be cleared by writing any data this byte. Or they also can be cleared by read this byte if register 0H bit 5 is 0”.
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
Bit
6:0
Bit
7
7
6
5
4
3
2
1
0
RWTO
Name
Name
RXFU
ROC
FOE
LCS
PLE
MF
RF
AE
CE
PHS0,RW
PHS0,RW
PHS0,RO
PHS0,RO
PHS0,RO
PHS0,RO
PHS0,RO
PHS0,RO
PHS0,RO
PHS0,RO
Default
Default
/C
/C
Runt Frame
It is set to indicate the received frame has the size smaller than 64 bytes.
Multicast Frame
It is set to indicate the received frame has a multicast address.
Late Collision Seen
It is set to indicate a late collision found during the frame reception.
Receive Watchdog Time-Out
It is set to indicate receive more than 2048 bytes.
Physical Layer Error
It is set to indicate a physical layer error found during the frame reception.
Alignment Error
It is set to indicate the received frame ends with a non-byte boundary.
CRC Error
It is set to indicate the received frame ends with a CRC error.
FIFO Overflow Error
It is set to indicate a FIFO Overflow error happens during the frame reception.
Receive Overflow Counter Overflow
This bit is set when the ROC has an overflow condition.
Receive Overflow Counter
This is a statistic counter to indicate the received packet count upon FIFO
overflow.
Description
Description
USB2.0 to Fast Ethernet Controller
DM9620
19

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