DM9620 DAVICOM [Davicom Semiconductor, Inc.], DM9620 Datasheet - Page 33

• Manufacturer Part Number: DM9620
• Description: USB2.0 to 10/100M Fast Ethernet Controller
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

6.3 PHY ID Identifier Register #1 (PHYID1) – 02H
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9620. The Identifier consists
of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model
revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E.
6.4 PHY Identifier Register #2 (PHYID2) – 03H
6.5 Auto-negotiation Advertisement Register(ANAR) – 04H
This register contains the advertised abilities of this DM9620 device as they will be transmitted to its link partner
during Auto-negotiation.
Preliminary
Version: DM9620 -15-DS-P02
February 20, 2012
15-10
15.0
9-4
3-0
Bit
Bit
Bit
15
14
1
0
Jabber detect
VNDR_MDL
MDL_REV
OUI_MSB
Bit Name
Bit Name
Bit Name
OUI_LSB
Extended
capability
ACK
NP
<101110>,
<001011>,
0,RO/LH
<0181h>
1,RO/P
<0000>,
Default
Default
Default
0,RO/P
RO/P
RO/P
RO/P
0,RO
0 = Link is not established
The link status bit is implemented with a latching function, so that
the occurrence of a link failure condition causes the link status bit to
be cleared and remain cleared until it is read via the management
interface
Jabber detect:
1 = Jabber condition detected
0 = No jabber
This bit is implemented with a latching function. Jabber conditions
will set this bit unless it is cleared by a read to this register through a
management interface or a PHY reset. This bit works only in
10Mbps mode
Extended capability:
1 = Extended register capable
0 = Basic register capable only
OUI most significant bits:
This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of
this register respectively. The most significant two bits of the OUI
are ignored (the IEEE standard refers to these as bit 1 and 2)
OUI least significant bits:
Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this
register respectively
Vendor model number:
Six bits of vendor model number mapped to bit 9 to 4 (most
significant bit to bit 9)
Model revision number:
Four bits of vendor model revision number mapped to bit 3 to 0
(most significant bit to bit 3)
Next page indication:
0 = No next page available
1 = Next page available
The PHY has no next page, so this bit is permanently set to 0
Acknowledge:
1 = Link partner ability data reception acknowledged
Description
Description
USB2.0 to Fast Ethernet Controller
Description
DM9620
33