W25Q16CLDAIG WINBOND [Winbond], W25Q16CLDAIG Datasheet - Page 15

• Manufacturer Part Number: W25Q16CLDAIG
• Description: 2.5V 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI
• Manufacturer: WINBOND [Winbond]

11.1.10 Quad Enable (QE)
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI
operation. When the QE bit is set to a 0 state (factory default), the /WP pin and /HOLD are enabled.
When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and /WP and /HOLD functions are
disabled.
WARNING: If the /WP or /HOLD pins are tied directly to the power supply or ground during
standard SPI or Dual SPI operation, the QE bit should never be set to a 1.
SECURITY REGISTER LOCK BITS
SECURITY REGISTER LOCK BITS
STATUS REGISTER PROTECT 0
STATUS REGISTER PROTECT 0
STATUS REGISTER PROTECT 1
STATUS REGISTER PROTECT 1
ERASE/WRITE IN PROGRESS
ERASE/WRITE IN PROGRESS
TOP/BOTTOM PROTECT
TOP/BOTTOM PROTECT
COMPLEMENT PROTECT
COMPLEMENT PROTECT
WRITE ENABLE LATCH
WRITE ENABLE LATCH
BLOCK PROTECT BITS
BLOCK PROTECT BITS
SECTOR PROTECT
SECTOR PROTECT
SUSPEND STATUS
SUSPEND STATUS
(non-volatile OTP)
(non-volatile OTP)
QUAD ENABLE
QUAD ENABLE
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
(non-volatile)
RESERVED
RESERVED
Figure 3a. Status Register-1
Figure 3b. Status Register-2
SRP0
SRP0
S7
S7
S15
S15
SUS
SUS
- 15 -
SEC
SEC
S6
S6
CMP
CMP
S14
S14
S5
S5
TB
TB
S13
S13
LB3
LB3
BP2
BP2
S4
S4
S12
S12
LB2
LB2
BP1
BP1
S3
S3
S11
S11
LB1
LB1
Publication Release Date: July 08, 2010
BP0
BP0
S2
S2
S10
S10
(R)
(R)
WEL BUSY
WEL BUSY
S1
S1
S9
S9
QE
QE
Preliminary - Revision A
SRP1
SRP1
S0
S0
W25Q16CL
S8
S8