NAND02GW3B2CN1F STMICROELECTRONICS [STMicroelectronics], NAND02GW3B2CN1F Datasheet - Page 17

• Manufacturer Part Number: NAND02GW3B2CN1F
• Description: 1 Gbit, 2 Gbit, 2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

NAND01G-B2B, NAND02G-B2C
4
4.1
4.2
4.3
4.4
Bus operations
There are six standard bus operations that control the memory. Each of these is described
in this section, see
Typically, glitches of less than 5 ns on Chip Enable, Write Enable and Read Enable are
ignored by the memory and do not affect bus operations.
Command Input
Command Input bus operations are used to give commands to the memory. Commands are
accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable
is Low and Read Enable is High. They are latched on the rising edge of the Write Enable
signal.
Only I/O0 to I/O7 are used to input commands.
See
Address Input
Address Input bus operations are used to input the memory addresses. Four bus cycles are
required to input the addresses for 1Gb devices whereas five bus cycles are required for the
2Gb device (refer to
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses.
See
Data Input
Data Input bus operations are used to input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal. The data is input sequentially using the Write Enable signal.
See
Data Output
Data Output bus operations are used to read: the data in the memory array, the Status
Register, the lock status, the Electronic Signature and the Unique Identifier.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low. The data is output sequentially using the Read Enable
signal.
See
Figure 19
Figure 20
Figure 21
Figure 22
and
and
and
and
Table 5: Bus
Table 24
Table 24
Table 24
Table 25
Table 6
for details of the timings requirements.
and
for details of the timings requirements.
and
for details of the timings requirements.
Operations, for a summary.
Table
Table 25
7, Address Insertion).
for details of the timings requirements.
Bus operations
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