HYB25D256160CC-5 QIMONDA [Qimonda AG], HYB25D256160CC-5 Datasheet - Page 28

• Manufacturer Part Number: HYB25D256160CC-5
• Description: 256-Mbit Double-Data-Rate SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1) 0 °C ≤
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
4) Inputs are not recognized as valid until
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
6) For each of the terms, if not already an integer, round to the next highest integer.
7)
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
11) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge. A valid transition
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
Rev. 2.3, 2007-03
03062006-8CCM-VPUW
Parameter
Internal write to read command
delay
Exit self-refresh to non-read
command
Exit self-refresh to read command
Parameter
DQ output access time from CK/CK
CK high-level width
Clock cycle time
CK low-level width
Auto precharge write recovery + precharge time
DQ and DM input hold time
DQ and DM input pulse width (each input)
DQS output access time from CK/CK
DQS input low (high) pulse width (write cycle)
other than CK/CK, is
t
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
between
is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW at this time, depending
on
performance (bus turnaround) degrades accordingly.
HZ
t
and
DQSS
T
t
.
A
LZ
V
≤ 70 °C
IH(ac)
transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
and
; V
V
DDQ
V
IL(ac)
REF
= 2.5 V ± 0.2 V,
.
. CK/CK slew rate are ≥ 1.0 V/ns.
Symbol
t
t
t
WTR
XSNR
XSRD
V
V
REF
DD
stabilizes.
= +2.5 V ± 0.2 V (DDR333);
–5
DDR400B
Min.
2
75
200
Symbol
t
t
t
t
t
t
t
t
t
AC
CH
CK
CL
DAL
DH
DIPW
DQSCK
DQSL,H
28
–7
DDR266A
Min.
–0.75
0.45
7.5
7.5
7.5
0.45
(
0.5
1.75
–0.75
0.35
t
WR
Max.
—
—
—
/
t
AC Timing - Absolute Specifications for PC2700
CK
V
)+(
DDQ
t
RP
= 2.6 V ± 0.1 V,
/
–6
DDR333
Min.
1
75
200
t
t
CK
CK
)
is equal to the actual systemclock cycle time.
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Max.
+0.75
0.55
12
12
12
0.55
—
—
—
+0.75
—
V
DD
= +2.6 V ± 0.1 V (DDR400)
Max.
—
—
—
Unit
ns
t
ns
ns
ns
t
t
ns
ns
ns
t
CK
CK
CK
CK
Unit Note/ Test
t
ns
t
Internet Data Sheet
CK
CK
Note/Test
Condition
2)3)4)5)
2)3)4)5)
CL = 3.0
CL = 2.5
CL = 2.0
2)3)4)5)
2)3)4)5)6)
2)3)4)5)
2)3)4)5)6)
2)3)4)5)
2)3)4)5)
TABLE 21
Condition
2)3)4)5)
2)3)4)5)
2)3)4)5)
V
TT
.
3)4)5)
2)3)4)5)
2)3)4)5)
1)
1)