W9864G6 WINBOND [Winbond], W9864G6 Datasheet
W9864G6
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W9864G6 Summary of contents
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... Self Refresh Command................................................................................................................... 10 Power Down Mode .......................................................................................................................... 10 No Operation Command ................................................................................................................. 11 Deselect Command......................................................................................................................... 11 Clock Suspend Mode ...................................................................................................................... 11 Table of Operating Modes............................................................................................................... 12 Simplified State Diagram................................................................................................................. CHARACTERISTICS .................................................................................................................. 14 Absolute Maximum Rating .............................................................................................................. 14 Recommended DC Operating Conditions....................................................................................... 14 Capacitance .................................................................................................................................... 14 1M × 4 BANKS × 16 BITS SDRAM Publication Release Date: January 27, 2003 - 1 - W9864G6DB Revision A1 ...
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... Timing Chart of Burst Stop Cycle (Burst Stop Command).............................................................. 42 Timing Chart of Burst Stop Cycle (Precharge Command).............................................................. 43 CKE/DQM Input Timing (Write Cycle)............................................................................................. 44 CKE/DQM Input Timing (Read Cycle) ............................................................................................ 45 Self Refresh/Power Down Mode Exit Timing .................................................................................. 46 12. PACKAGE DIMENSIONS ............................................................................................................... 47 BGA 60 Balls Pitch = 0.65 mm........................................................................................................ 47 13. VERSION HISTORY ....................................................................................................................... W9864G6DB ...
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... Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time. By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9864G6DB is ideal for main memory in high performance applications. 2. FEATURES 2.7V − ...
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... VDD WE# WE# LDQM CAS# CAS# RAS# CS# CS# NC BS0 BS0 BS1 A10 A10 VDD VDD W9864G6DB Bottom View 2 1 DQ0 DQ15 VSS VDDQ VSSQ DQ14 VSSQ VDDQ DQ13 DQ4 DQ11 DQ12 VDDQ VSSQ DQ10 VSSQ VDDQ DQ9 NC NC DQ8 ...
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... Power (+3.3V) Power for input buffers and logic circuit inside DRAM. Ground for input buffers and logic circuit inside Ground DRAM. Power (+3.3V) Separated power from V for I/O Buffer immunity. Ground for I/O Separated ground from V Buffer immunity. No Connection No connection Publication Release Date: January 27, 2003 - 5 - W9864G6DB DESCRIPTION , to improve DQ noise improve DQ noise SS Revision A1 ...
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... COLUMN DECODER CELL ARRAY BANK #0 SENSE AMPLIFIER DATA CONTROL CIRCUIT COLUMN DECODER CELL ARRAY BANK #2 SENSE AMPLIFIER NOTE: The cell array configuration is 2048 * 256 * W9864G6DB COLUMN DECODER CELL ARRAY BANK #1 SENSE AMPLIFIER DQ0 DQ BUFFER DQ15 UDQM LDQM COLUMN DECODER CELL ARRAY ...
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... DDQ supplies. After power up, an initial pause of 200 µS is required DD ). The maximum time that each bank can be held active is RRD - 7 - W9864G6DB delay. WE pin voltage level RCD Publication Release Date: January 27, 2003 Revision A1 +0.3V DD has RSC ) ...
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... A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop - 8 - W9864G6DB ...
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... No address carry from ACCESS ADDRESS W9864G6DB BURST LENGTH BUST LENGTH Publication Release Date: January 27, 2003 Revision A1 ...
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... The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down mode longer than the Refresh period (t device. ) has been satisfied. Issue of Auto DAL DPL (min). RAS - 10 - W9864G6DB and t are satisfied. DPL RP ). When using the Auto-precharge the REF ...
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... While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. W9864G6DB . The input buffers need (min ...
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... W9864G6DB A10 A0−A9 CS RAS CAS ...
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... REF IDLE Power Down CKE Active ROW Power ACTIVE Down CKE Read WRITE READ Write READA WRITEA Precharge Precharge Publication Release Date: January 27, 2003 - 13 - W9864G6DB CBR Refresh Read CKE READ SUSPEND CKE CKE READA SUSPEND CKE Automatic sequence Manual input Revision A1 ...
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... DD, DDQ T OPR T -55 − 150 STG T SOLDER OUT SYM. MIN 2.7 DDQ DQM, CKE) RAS CAS W9864G6DB RATING UNIT V +0 − 70 °C °C 260 ° TYP. MAX. UNIT 3.3 3.6 V 3 0.8 V SYM. MIN. ...
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... IH CKE = V (Power IL I Down mode) CKE = V IH CKE = V (Power IL Down mode min min.) CK SYMBOL W9864G6DB -7 SYM. UNIT MAX CC1 I 30 CC2 I 1 CC2P I 8 CC2S mA 1 CC2PS I 55 CC3 I 5 CC3P I 145 CC4 I 110 ...
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... CL tWR CL CL tCK CL tCH tCL CL tAC CL tOH tHZ tLZ tSB tT tDS tDH tAS tAH tCKS tCKH tCMS tCMH tREF tRSC - 16 - W9864G6DB -7 UNIT MIN. MAX 100000 Cycle 1000 7 1000 5 ...
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... CLK measured from the negative edge to the positive edge referenced (simultaneously) while all input signals are held in the “NOP” state. The CLK DDQ 1 ohms AC TEST LOAD and W9864G6DB CONDITIONS 1.4V See diagram below 2.4V/0. 1.4V 50 ohms 50pF Publication Release Date: January 27, 2003 Revision A1 (min.). IH (max.). IL ...
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... Read with Auto Precharge Command to Active/Ref Command Write with Auto Precharge Command to Active/Ref Command W9864G6DB 1 Cycle Cycle + ...
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... RAS CAS WE A0-A10 BS0 CKS CKH CKE t t CMS CMH t t CMS CMH t t CMS CMH t t CMS CMH CKS CKH t CKS Publication Release Date: January 27, 2003 - 19 - W9864G6DB CMH CMS t CKH Revision A1 ...
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... Timing Waveforms, continued Read Timing CLK CS RAS CAS WE A0-A10 BS0 Read Command Read CAS Latency Valid Data-Out - 20 - W9864G6DB Valid Data-Out Burst Length ...
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... Valid Data- Valid Data- Valid Data- Valid Data-in Publication Release Date: January 27, 2003 - 21 - W9864G6DB t t CMH CMS Valid Valid Data-in Data- Valid Data- Valid ...
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... OH Valid Valid Data-Out Data-Out Valid Valid Data-Out Data-Out Valid Valid Data-Out Data-Out Valid Valid Data-Out Data-Out - 22 - W9864G6DB OPEN Valid Data-Out OPEN Valid Data-Out ...
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... CAS Latency "0" (Test Mode) A8 "0" Reserved A9 A0 Write Mode A0 "0" A10 "0" A11 A0 Reserved A0 BS0 "0" BS1 A0 "0" W9864G6DB t RSC command A0 Burst Length Sequential A0 Interleave ...
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... RP t RAS t t RCD RCD RBb RAc RBb CBx RAc t AC bx1 aw0 aw2 aw3 bx0 aw1 t t RRD Active Precharge Active Read Precharge - 24 - W9864G6DB RAS RAS t RCD RBd CAy RBd CBz t ...
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... RAS t RCD t RCD RAc CBx RAc aw0 aw1 aw2 aw3 bx0 bx1 t RRD AP* Active Read AP W9864G6DB RAS RAS t RCD RAe RBd CAy CBz RAe RBd ...
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... RP RAS t RCD RBb RBb CBy ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 t RRD Precharge Active Read - 26 - W9864G6DB RAS t RCD RAc RAc CAz t AC by1 by4 by5 by6 by7 CZ0 Active Read Precharge ...
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... RAS RP t RCD RBb RBb CBy t CAC ax3 ax4 ax0 ax1 ax2 ax5 ax6 ax7 t RRD AP* Active Read * AP is the internal precharge start timing - 27 - W9864G6DB RAS t RCD RAc RAc CAz t CAC t CAC by0 by1 by4 by5 ...
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... RC t RAS t RCD RBb RBb CBy ax4 ax5 ax6 ax7 by0 by1 by2 t RRD Precharge Active Write - 28 - W9864G6DB RAS t RCD RAc RAc CAz by3 by4 by5 by6 by7 CZ0 CZ1 Active Write ...
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... RC t RAS t RCD RBb CBy RBb ax4 by2 ax5 ax6 ax7 by0 by1 by3 t RRD AP* Active Write * AP is the internal precharge start timing - 29 - W9864G6DB RAS t RCD RAb CAz RAc by5 by4 by6 by7 CZ0 CZ1 ...
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... RAS t RAS t RCD CBx CAy CAm bx0 Ay0 Ay1 a2 bx1 Read Read Read * AP is the internal precharge start timing - 30 - W9864G6DB CBz am1 am2 bz0 bz1 bz2 bz3 Ay2 am0 Precharge AP* Read 23 ...
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... MHz RAS CAy t AC ax5 ax0 ax1 ax3 ay0 ax2 ax4 Write - 31 - W9864G6DB ay1 ay2 ay4 ay3 Precharge Publication Release Date: January 27, 2003 Revision ...
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... Idle Bank #3 (CLK = 100 MHz RCD RAb RAb t AC aw0 aw1 aw2 aw3 AP* Active * AP is the internal precharge start timing - 32 - W9864G6DB RAS CAx t AC bx1 bx2 bx3 bx0 Read AP* 23 ...
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... RCD RAb RAb CAx bx0 aw2 aw3 Active Write AP the internal precharge start timing Publication Release Date: January 27, 2003 - 33 - W9864G6DB RAS RP RAc RAc bx1 bx3 bx2 Active AP* Revision A1 23 ...
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... Operating Timing Example, continued Auto Refresh Cycle CLK RAS CAS WE BS0,1 A10 A0-A9 DQM CKE DQ All Banks Auto Prechage Refresh (CLK = 100 MHz W9864G6DB Auto Refresh (Arbitrary Cycle) ...
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... BS0,1 A10 A0-A9 DQM t CKE t CKS DQ All Banks Self Refresh Precharge Entry (CLK = 100 MHz CKS SB Self Refresh Cycle - 35 - W9864G6DB CKS Operation Cycle Arbitrary Cycle Publication Release Date: January 27, 2003 Revision A1 23 ...
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... Bank #1 Bank #2 Idle Bank #3 (CLK = 100 MHz CBw CBx CBy t AC av0 av1 av3 aw0 ax0 av2 Single Write - 36 - W9864G6DB CBz t AC ay0 az0 az1 az2 az3 Read 23 ...
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... When CKE goes high, command input must be No operation at next CLK rising edge. (CLK = 100 MHz CAa t CKS ax0 ax2 ax3 ax1 Precharge Read Publication Release Date: January 27, 2003 - 37 - W9864G6DB RAa RAa CAx CKS NOPActive Precharge Standby Power Down mode Revision A1 ...
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... Act Act represents the Write with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command W9864G6DB Act Act AP Act ...
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... Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. Publication Release Date: January 27, 2003 - 39 - W9864G6DB Act Act AP Act (min) ...
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... Command DQM DQ (2) CAS Latency Command DQM Command DQM DQ Note: The Output data must be masked by DQM to avoid I/O conflict Read Write Read Write Read Write Read Write W9864G6DB ...
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... Command DQM D0 DQ Write ( b ) Command DQM D0 DQ (2) CAS Latency = 3 Write ( a ) Command DQM D0 DQ Write ( b ) Command DQM Read Read Read Q0 Q1 Read Q0 D1 Publication Release Date: January 27, 2003 - 41 - W9864G6DB Revision A1 ...
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... Timing Chart of Burst Stop Cycle (Burst Stop Command (3) Read cycle ( a ) CAS latency =2 Read Command CAS latency = 3 Read Command DQ (2) Write cycle Write Command Note: BST BST BST BST represents the Burst stop command - 42 - W9864G6DB ...
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... DQM CAS latency = 3 Write Commad DQM D0 DQ PRCG Note PRCG PRCG PRCG PRCG represents the Precharge command - 43 - W9864G6DB Publication Release Date: January 27, 2003 Revision A1 11 ...
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... External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM DQM MASK ( DQM MASK ( CKE MASK ( W9864G6DB CKE MASK CKE MASK ...
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... External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM Publication Release Date: January 27, 2003 - 45 - W9864G6DB Open Open Open Revision A1 ...
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... All Input Buffer (Include CLK Buffer) are turned off in the Power Down mode and Self Refresh mode NOP Represents the No-Operation command Command Represents one command (min (min)+t (min) CKS CK Command Input Buffer Enable (min (min)+t (min) CKS CK Command Input Buffer Enable - 46 - W9864G6DB (min (min ...
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... PACKAGE DIMENSIONS BGA 60 Balls Pitch = 0.65 mm W9864G6DB Publication Release Date: January 27, 2003 - 47 - Revision A1 ...
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... TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 - 48 - W9864G6DB DESCRIPTION Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No ...