HYB18T512400BF-2.5 QIMONDA [Qimonda AG], HYB18T512400BF-2.5 Datasheet - Page 30

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HYB18T512400BF-2.5

Manufacturer Part Number
HYB18T512400BF-2.5
Description
512-Mbit Double-Data-Rate-Two SDRAM
Manufacturer
QIMONDA [Qimonda AG]
Datasheet
1)
2)
3)
4) The value of
5) The value of
Rev. 1.1, 2007-05
03292006-YBYM-WG0Z
Symbol
V
V
V
V
V
IN(dc)
ID(dc)
ID(ac)
IX(ac)
OX(ac)
V
V
V
indicates the voltage at which differential input signals must cross.
indicates the voltage at which differential input signals must cross.
IN(dc)
ID(dc)
ID(ac)
specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.
specifies the input differential voltage
specifies the input differential voltage
Parameter
DC input signal voltage
DC differential input voltage
AC differential input voltage
AC differential cross point input voltage
AC differential cross point output voltage 0.5 ×
V
V
IX(ac)
OX(ac)
is expected to equal 0.5 ×
is expected to equal 0.5 ×
V
V
TR
TR
V
V
DDQ
DDQ
V
V
CP
of the transmitting device and
CP
of the transmitting device and
required for switching. The minimum value is equal to
required for switching. The minimum value is equal to
–0.3
0.5 ×
Min.
0.25
0.5
Differential DC and AC Input and Output Logic Levels
30
V
V
DDQ
DDQ
Single-ended AC Input Test Conditions Diagram
– 0.175
– 0.125
V
V
IX(ac)
OX(ac)
512-Mbit Double-Data-Rate-Two SDRAM
is expected to track variations in
Max.
V
V
V
0.5 ×
0.5 ×
is expected to track variations in
DDQ
DDQ
DDQ
+ 0.3
+ 0.6
+ 0.6
V
V
DDQ
DDQ
HYB18T512[40/80/16]0B[C/F]
+ 0.175
+ 0.125
V
V
IH(dc)
IH(ac)
Internet Data Sheet
V
Unit
V
V
V
TABLE 30
V
FIGURE 4
IL(dc)
IL(ac)
V
.
DDQ
.
V
DDQ
.
V
.
Note
1)
2)
3)
4)
5)
IX(ac)
V
OX(ac)

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