HYB18T512400BF-2.5 QIMONDA [Qimonda AG], HYB18T512400BF-2.5 Datasheet - Page 54

• Manufacturer Part Number: HYB18T512400BF-2.5
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
Rev. 1.1, 2007-05
03292006-YBYM-WG0Z
Parameter
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh
command period
Precharge-All (4 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command
period
Active bank A to Active bank B command
period
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without Auto-
Precharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit active power-down mode to Read
command (slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
Write recovery time for write with Auto-
Precharge
V
and then restarted through the specified initialization sequence before normal operation can continue.
DDQ
= 1.8 V ± 0.1 V;
V
DD
= 1.8 V ±0.1 V.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
—
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WR
HP
HZ
IH
IPW
IS
LZ(DQ)
LZ(DQS)
MRD
OIT
QH
QHS
REFI
REFI
RP
RPRE
RPST
RRD
RRD
RTP
WPRE
WPST
WR
WTR
XARD
XARDS
XP
XSNR
XSRD
(base)
(base)
54
DDR2–400
MIN. (
—
475
0.6
350
2 ×
t
2
0
t
—
—
—
105
t
0.9
0.40
7.5
10
7.5
0.25
0.40
15
10
2
6 – AL
2
t
200
t
Min.
AC.MIN
HP
RP
RFC
WR
–
/
t
t
AC.MIN
t
+10
CK
QHS
t
CL,
t
CH
)
512-Mbit Double-Data-Rate-Two SDRAM
Max.
t
—
—
—
t
t
—
12
—
450
7.8
3.9
—
—
1.1
0.60
—
—
—
—
0.60
—
—
—
—
—
—
—
—
AC.MAX
AC.MAX
AC.MAX
HYB18T512[40/80/16]0B[C/F]
Unit
—
ps
ps
t
ps
ps
ps
t
ns
—
ps
µs
µs
ns
ns
t
t
ns
ns
ns
t
t
ns
ns
t
t
t
ns
t
t
Internet Data Sheet
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
Note
1)2)3)4)5)6)
11)
12)
10)
10)
13)
13)
13)14)
15)17)
16)
13)
13)
13)17)
15)21)
18)
19)
20)
20)
21)