HYB18T512400BF-2.5 QIMONDA [Qimonda AG], HYB18T512400BF-2.5 Datasheet - Page 52

• Manufacturer Part Number: HYB18T512400BF-2.5
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
5) Inputs are not recognized as valid until
6) The output timing reference voltage level is
7) For each of the terms, if not already an integer, round to the next highest integer.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
9) For timing definition, refer to the Component data sheet.
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
11) MIN (
12) The
Rev. 1.1, 2007-05
03292006-YBYM-WG0Z
Parameter
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh
command period
Precharge-All (4 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command
period
Active bank A to Active bank B command
period
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without Auto-
Precharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit active power-down mode to Read
command (slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
Write recovery time for write with Auto-
Precharge
V
and then restarted through the specified initialization sequence before normal operation can continue.
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
input reference level is the crosspoint when in differential strobe mode.
the WR parameter stored in the MR.
mis-match between DQS / DQS and associated DQ in any given cycle.
be greater than the minimum specification limits for
(
parameters are verified by design and characterization, but not subject to production test.
t
HZ,
DDQ
t
t
HZ
RPST
t
= 1.8 V ± 0.1 V;
CL
,
,
t
RPST
), or begins driving (
t
CH
) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
and
t
LZ
,
t
V
RPRE
DD
= 1.8 V ±0.1 V.
parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
t
LZ,
t
RPRE
).
V
t
HZ
REF
and
V
stabilizes. During the period before
TT
.
t
LZ
transitions occur in the same access time windows as valid data transitions.These
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WR
REFI
RFC
RP
RPRE
RPST
RRD
RRD
RTP
WPRE
WPST
WR
WTR
XARD
XARDS
XP
XSNR
XSRD
t
CL
and
t
CH
).
52
DDR2–533
—
105
t
0.9
0.40
7.5
10
7.5
0.25
0.40
15
7.5
2
6 – AL
2
t
200
t
Min.
RP
RFC
WR
/
t
+10
CK
V
t
REF
CK
512-Mbit Double-Data-Rate-Two SDRAM
refers to the application clock period. WR refers to
stabilizes, CKE = 0.2 x
Max.
3.9
—
—
1.1
0.60
—
—
—
—
0.60
—
—
—
—
—
—
—
—
HYB18T512[40/80/16]0B[C/F]
V
DDQ
Unit
µs
ns
ns
t
t
ns
ns
ns
t
t
ns
ns
t
t
t
ns
t
t
Internet Data Sheet
CK
CK
CK
CK
CK
CK
CK
CK
CK
is recognized as low.
Note
1)2)3)4)5)6)
15)17)
16)
13)
13)
13)17)
15)21)
18)
19)
20)
20)
21)