PSD4235G2-12UIT STMICROELECTRONICS [STMicroelectronics], PSD4235G2-12UIT Datasheet - Page 29

• Manufacturer Part Number: PSD4235G2-12UIT
• Description: Flash in-system programmable (ISP) peripherals for 16-bit MCUs (3.3 V supply)
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

PSD4235G2V
5.17
PLD Array WRH
VM register
Table 24.
On reset, bit1-Bit4 are loaded to configurations that are selected by the user in PSDsoft
Express. bit0 and bit7 are always cleared on reset. bit0-Bit4 are active only when the device
is configured in Philips 80C51XA mode.
SR_code
Boot_code
FL_code
Boot_data
FL_data
Peripheral mode
Bit 7
Peripheral
mode
0: WRH/DBE input to the PLD AND array is connected.
1: WRH/DBE input to the PLD AND array is disconnected, saving power.
0 = PSEN cannot access SRAM in 80C51XA modes.
1 = PSEN can access SRAM in 80C51XA modes.
0 = PSEN cannot access secondary NVM in 80C51XA modes.
1 = PSEN can access secondary NVM in 80C51XA modes.
0 = PSEN cannot access primary Flash memory in 80C51XA modes.
1 = PSEN can access primary Flash memory in 80C51XA modes.
0 = RD cannot access secondary NVM in 80C51XA modes.
1 = RD can access secondary NVM in 80C51XA modes.
0 = RD cannot access primary Flash memory in 80C51XA modes.
1 = RD can access primary Flash memory in 80C51XA modes.
0 = Peripheral mode of Port F is disabled.
1 = Peripheral mode of Port F is enabled.
Bit 6
not used
(set to ’0’)
VM register
Bit 5
not used
(set to ’0’)
Bit 4
FL_data
Bit 3
Boot_data FL_code
Bit 2
Register bit definition
Bit 1
Boot_code SR_code
Bit 0
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