PSD4235G2-12UIT STMICROELECTRONICS [STMicroelectronics], PSD4235G2-12UIT Datasheet - Page 79

• Manufacturer Part Number: PSD4235G2-12UIT
• Description: Flash in-system programmable (ISP) peripherals for 16-bit MCUs (3.3 V supply)
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

PSD4235G2V
Table 40.
1. N/A = Not Applicable.
19.6
19.7
19.8
80C51XA
All other MCU with
multiplexed bus
MCU
I/O port latched address output assignments
Address In mode
For MCUs that have more than 16 address signals, the higher addresses can be connected
to Port A, B, C, D or F, and are routed as inputs to the PLDs. The address input can be
latched in the input macrocell (IMC) by Address Strobe (ALE/AS, PD0). Any input that is
included in the DPLD equations for the primary Flash memory, secondary Flash memory or
SRAM is considered to be an address input.
Data Port mode
Ports F and G can be used as a data bus port for a MCU with a non-multiplexed
address/data bus. The Data Port is connected to the data bus of the MCU. The general I/O
functions are disabled in Ports F and G if the ports are configured as a Data Port. Data Port
mode is automatically configured in PSDsoft Express when a non-multiplexed bus MCU is
selected.
Peripheral I/O mode
Peripheral I/O mode can be used to interface with external 8-bit peripherals. In this mode, all
of Port F serves as a tri-state, bi-directional data buffer for the MCU. Peripheral I/O mode is
enabled by setting bit 7 of the VM register to a '1.'
directional buffer for the MCU data bus if Peripheral I/O mode is enabled. An equation for
PSEL0 and/or PSEL1 must be specified in PSDsoft Express. The buffer is tri-stated when
PSEL0 or PSEL1 is not active.
(PE3-PE0)
Address
Port E
a3-a0
N/A
(PE7-PE4)
Address
Address
Port E
a7-a4
a7-a4
(PF3-PF0)
Address
Port F
a3-a0
N/A
(1)
Figure 27
(PF7-PF4)
Address
Address
Port F
a7-a4
a7-a4
shows how Port A acts as a bi-
(PG3-PG0)
Address
Address
a11-a8
a11-a8
Port G
(PG7-PG4)
Address
a15-a12
Address
a15-a12
Port G
I/O ports
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