PSD4235G2-12UIT STMICROELECTRONICS [STMicroelectronics], PSD4235G2-12UIT Datasheet - Page 92

• Manufacturer Part Number: PSD4235G2-12UIT
• Description: Flash in-system programmable (ISP) peripherals for 16-bit MCUs (3.3 V supply)
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Power management
20.5
20.6
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PSD Chip Select input (CSI, PD2)
PD2 of Port D can be configured in PSDsoft Express as PSD Chip Select input (CSI). When
low, the signal selects and enables the internal primary Flash memory, secondary Flash
memory, SRAM, and I/O blocks for READ or WRITE operations involving the PSD. A high on
PSD Chip Select input (CSI, PD2) disables the primary Flash memory, secondary Flash
memory, and SRAM, and reduces the PSD power consumption. However, the PLD and I/O
signals remain operational when PSD Chip Select input (CSI, PD2) is high.
There may be a timing penalty when using PSD Chip Select input (CSI, PD2) depending on
the speed grade of the PSD that you are using. See the timing parameter t
Input clock
The PSD provides the option to turn off CLKIN (PD1) to the PLD to save AC power
consumption. CLKIN (PD1) is an input to the PLD AND Array and the output macrocells
(OMC).
During Power-down mode, or, if CLKIN (PD1) is not being used as part of the PLD logic
equation, the clock should be disabled to save AC power. CLKIN (PD1) is disconnected from
the PLD AND Array or the macrocells block by setting bits 4 or 5 to a ’1’ in PMMR0.
Figure 32. Enable Power-down flowchart
No
by setting PMMR0 bits 4 and 5
Disable desired inputs to PLD
and PMMR2 bits 0 to 6.
Set PMMR0 Bit 1 = 1
PSD in Power
OPTIONAL
for 15 CLKIN
Enable APD
ALE/AS idle
Down Mode
clocks?
RESET
Yes
AI04940
SLQV
PSD4235G2V
in
Table
68.