PSD4235G2-12UIT STMICROELECTRONICS [STMicroelectronics], PSD4235G2-12UIT Datasheet - Page 57

• Manufacturer Part Number: PSD4235G2-12UIT
• Description: Flash in-system programmable (ISP) peripherals for 16-bit MCUs (3.3 V supply)
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

PSD4235G2V
Figure 13. Macrocell and I/O port
17.1
Output macrocell (OMC)
Eight of the output macrocells (OMC) are connected to Ports A pins and are named as
McellA0-McellA7. The other eight macrocells are connected to Ports B pins and are named
as McellB0-McellB7.
The output macrocell (OMC) architecture is shown in
there are native product terms available from the AND Array, and borrowed product terms
available (if unused) from other output macrocells (OMC). The polarity of the product term is
controlled by the XOR gate. The output macrocell (OMC) can implement either sequential
logic, using the flip-flop element, or combinatorial logic. The multiplexer selects between the
sequential or combinatorial logic outputs. The multiplexer output can drive a port pin and
has a feedback path to the AND Array inputs.
The flip-flop in the output macrocell (OMC) block can be configured as a D, T, JK, or SR type
in the PSDsoft Express program. The flip-flop’s clock, preset, and clear inputs may be driven
from a product term of the AND Array. Alternatively, the external CLKIN (PD1) signal can be
used for the clock input to the flip-flop. The flip-flop is clocked on the rising edge of CLKIN
(PD1). The preset and clear are active high inputs. Each clear input can use up to two
product terms.
PRODUCT TERMS
MACROCELLS
FROM OTHER
PRODUCT TERM
PT CLEAR
GLOBAL
CLOCK
CLOCK
SELECT
ALLOCATOR
PRODUCT TERMS
PT
CLOCK
PT INPUT LATCH GATE/CLOCK
CPLD MACROCELLS
UP TO 10
POLARITY
SELECT
PT OUTPUT ENABLE ( OE )
MACROCELL FEEDBACK
I/O PORT INPUT
PT PRESET
CK
PR DI LD
D/T/JK FF
D/T
SELECT
MCU ADDRESS / DATA BUS
MCU DATA IN
CL
Q
MCU LOAD
SELECT
COMB.
/REG
CONTROL
MACROCELL
LOAD
OUT TO
DATA
MCU
Figure
ALE/AS
I/O PORTS
ADDRESS OUT
DATA
CPLD OUTPUT
WR
INPUT MACROCELLS
WR
PDR
LATCHED
14. As shown in the figure,
D
D
REG.
INPUT
DIR
Q
Q
Complex PLD (CPLD)
MUX
SELECT
Q
Q D
D
G
AI04945
I/O PIN
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