PSD4235G2V-10U STMICROELECTRONICS [STMicroelectronics], PSD4235G2V-10U Datasheet - Page 17

• Manufacturer Part Number: PSD4235G2V-10U
• Description: Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

In-System Programming (ISP)
Using the JTAG signals on Port E, the entire PSD
device (memory, logic, configuration) can be pro-
grammed or erased without the use of the MCU.
In-Application Programming (IAP)
The primary Flash memory can also be pro-
grammed, or re-programmed, in-system by the
MCU executing the programming algorithms out of
the secondary Flash memory, or SRAM. The sec-
ondary Flash memory can be programmed the
same way by executing out of the primary Flash
memory. Table 5, page 17 indicates which pro-
gramming methods can program different func-
tional blocks of the PSD.
Page Register
The 8-bit Page Register expands the address
range of the MCU by up to 256 times. The paged
address can be used as part of the address space
to access external memory and peripherals, or in-
ternal memory and I/O. The Page Register can
also be used to change the address mapping of
Table 5. Methods of Programming Different Functional Blocks of the PSD
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Primary Flash Memory
Secondary Flash memory
PLD Array (DPLD and CPLD)
PSD Configuration
Functional Block
JTAG-ISP
Yes
Yes
Yes
Yes
the Flash memory blocks into different memory
spaces for IAP.
Power Management Unit (PMU)
The Power Management Unit (PMU) gives the
user control of the power consumption on selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
mode that helps reduce power consumption.
The PSDalso has some bits that are configured at
run-time by the MCU to reduce power consump-
tion of the CPLD. The Turbo Bit in PMMR0 can be
reset to ’0’ and the CPLD latches its outputs and
goes to Standby Mode until the next transition on
its inputs.
Additionally, bits in PMMR2 can be set by the
MCU to block signals from entering the CPLD to
reduce power consumption. See the section enti-
tled “POWER MANAGEMENT” on page 70 for
more details.
Device Programmer
Yes
Yes
Yes
Yes
PSD4256G6V
IAP
Yes
Yes
No
No
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