PSD4235G2V-10U STMICROELECTRONICS [STMicroelectronics], PSD4235G2V-10U Datasheet - Page 93

• Manufacturer Part Number: PSD4235G2V-10U
• Description: Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Table 69. Port F Peripheral Data Mode WRITE Timing
Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
Table 70. Power-down Timing
Table 71. Reset (RESET) Timing
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
Figure 48. Reset (RESET) Timing Diagram
Table 72. V
Note: 1. V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Symbol
t
t
t
t
t
t
Symbol
WHQZ–PF
CLWH
Symbol
Symbol
WLQV–PF
NLNH–PO
DVQV–PF
t
LVDV
NLNH–A
t
t
t
V
t
RESET
NLNH
BVBH
BXBL
2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
3. Any input used to select Port F Data Peripheral mode.
4. Data is already stable on Port F.
5. Data stable on ADIO pins to data on Port F.
OPR
2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.
CC
STBYON
ALE Access Time from Power-down
Maximum Delay from APD Enable to
Internal PDN Valid Signal
STBYON
WR to Data Propagation Delay
Data to Port A Data Propagation Delay
WR Invalid to Port A Tri-state
RESET Active Low Time
Power-on RESET Active Low Time
Warm RESET Active Low Time
RESET High to Operational Device
V
V
Low
timing is measured at V
STBY
STBY
Detection to V
Off Detection to V
Timing
Power-On Reset
V
Parameter
t NLNH-PO
CC
(min)
Parameter
Parameter
Parameter
STBYON
CC
ramp rate of 2ms.
STBYON
1
Output High
2
Output
t OPR
Using CLKIN
Conditions
Conditions
(PD1)
(Note
(Note
(Note
Conditions
Conditions
(Note
(Note
2
5
2
)
)
)
1
1
)
)
Min
Min
Min
Warm Reset
t NLNH-A
Min
300
t NLNH
25
1
15 * t
-10
-10
CLCL
Typ
20
20
1
Max
Max
128
PSD4256G6V
40
35
33
Max
300
t OPR
Max
AI02866b
93/100
Unit
Unit
Unit
Unit
ms
ns
ns
ns
ns
µs
ns
ns
µs
µs
s