PSD4235G2V-10U STMICROELECTRONICS [STMicroelectronics], PSD4235G2V-10U Datasheet - Page 53

• Manufacturer Part Number: PSD4235G2V-10U
• Description: Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

80C51XA
The Philips 80C51XA MCU has a 16-bit multi-
plexed bus with burst cycles. Address bits (A3-A1)
are not multiplexed, while (A19-A4) are multi-
plexed with data bits (D15-D0).
The PSD4256G6V supports the 80C51XA burst
mode. The WRH signal is connected to PD3, and
WHL is connected to CNTL0. The RD and PSEN
signals are connected to the CNTL1 and CNTL2
pins. Figure 23 shows the schematic diagram.
Figure 23. Interfacing the PSD with an 80C51XA-G3
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
RESET\
U3
CRYSTAL
RESET\
VCC_BAR
21
20
11
13
16
10
14
15
35
17
6
7
9
8
XA-G3
XTAL1
XTAL2
RXD0
TXD0
RXD1
TXD1
T2EX
T2
T0
RST
INT0
INT1
EA/WAIT
BUSW
A14D10
A15D11
A16D12
A17D13
A18D14
A19D15
A0/WRH
A10D6
A11D7
A12D8
A13D9
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
PSEN
WRL
ALE
RD
A3
A2
A1
43
42
41
40
39
38
37
36
24
25
26
27
28
29
30
31
5
4
3
2
18
19
32
33
A3
A2
A1
WRH\
WRL\
RD\
PSEN\
ALE
The 80C51XA improves bus throughput and per-
formance by issuing burst cycles to retrieve codes
from memory. In burst cycles, address A19-A4 are
latched internally by the PSD, while the 80C51XA
drives the A3-A1 signals to retrieve sequentially up
to 16 bytes of code. The PSD access time is then
measured from address A3-A1 valid to data in val-
id. The PSD bus timing requirement in a burst cy-
cle is identical to the normal bus cycle, except the
address setup and hold time with respect to Ad-
dress Strobe (ALE/AS, PD0) is not required.
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12D8
A13D9
A14D10
A15D11
A16D12
A17D13
A18D14
A19D15
10
11
12
13
14
15
16
17
18
19
20
59
60
40
79
80
39
71
72
73
74
75
76
77
78
3
4
5
6
7
1
2
PSD
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0(WR)
CNTL1(RD)
CNTL2(PSEN)
PD0 (ALE)
PD1 (CLKIN)
PD2 (CSI)
PD3 (WRH)
RESET
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
VCC_BAR
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
31
32
33
34
35
36
37
38
21
22
23
24
25
26
27
28
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
PSD4256G6V
D[15:0]
A[3:1]
A1
A2
A3
AI04952b
53/100
D[15:0]
A[3:1]