PSD4235G2V-10U STMICROELECTRONICS [STMicroelectronics], PSD4235G2V-10U Datasheet - Page 91

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PSD4235G2V-10U

Manufacturer Part Number
PSD4235G2V-10U
Description
Flash In-System Programmable (ISP) Peripherals for 16-bit MCUs
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
Table 67. WRITE Timing
Note: 1. Any input used to select an internal PSD function.
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Symbol
t
t
t
t
t
WHAX1
WHAX2
t
t
t
t
t
t
t
t
t
WHDX
WLWH
WHPV
WLMV
DVWH
DVMV
AVWL
SLWL
LXAX
AVPV
AVLX
LVLX
2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
3. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active WRITE signal.
5. Assuming WRITE is active before data becomes valid.
6. tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
7. tWHAX is 11 ns when writing to the Output Macrocell Registers.
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
Address Valid to Leading
Edge of WR
CS Valid to Leading Edge of WR
WR Data Setup Time
WR Data Hold Time
WR Pulse Width
Trailing Edge of WR to Address Invalid
Trailing Edge of WR to DPLD Address
Invalid
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
Data Valid to Port Output Valid
Using Macrocell Register Preset/Clear
Address Input Valid to Address
Output Delay
WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear
Parameter
Conditions
(Notes
(Notes
(Notes
(Note
(Note
(Note
(Note
(Note
(Note
(Note
(Note
(Note
(Note
3,7
3,6
1,3
3,5
3,4
1
1
3
3
3
3
3
2
)
)
)
)
)
)
)
)
)
)
)
)
)
Min
22
15
15
40
40
7
8
5
8
0
-10
Max
PSD4256G6V
45
65
35
65
91/100
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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