STC4130-I ETC2 [List of Unclassifed Manufacturers], STC4130-I Datasheet

STC4130-I

Manufacturer Part Number

STC4130-I

Description

Synchronous Clock for SETS

Manufacturer

ETC2 [List of Unclassifed Manufacturers]

Datasheet

1.STC4130-I.pdf (44 pages)

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Description

The STC4130 is a ROHS compatible, integrated,

single chip solution for the synchronous clock in SDH

and SONET network elements. The device is fully

compliant with ITU-T G.812 Type III, G.813, and

Telcordia GR1244, and GR253.

The STC4130 accepts 12 reference inputs and gen-

erates 8 independent synchronized output clocks.

Reference

detected, and inputs are individually monitored for

quality. Active reference selection may be manual or

automatic. All reference switches are hitless. Syn-

chronized outputs may be programmed for a wide

variety of SONET and SDH frequencies.

Two independent clock generators provide the stan-

dardized T0 and T4 functions. Each clock generator

includes a DPLL (Digital Phase-Locked Loop), which

may operate in the Freerun, Synchronized, and Hold-

over modes. Both clock generators support master/

slave operation for redundant applications. Connor-

Winfield’s proprietary SyncLink

link provides master/slave phase information and

state data to ensure seamless side switches.

A standard SPI serial bus interface or parallel bus

provide access to the STC4130’s comprehensive, yet

simple to use internal control and status registers.

The device operates with an external OCXO or TCXO

as its MCLK at either 10 or 20 MHz.

input

T0_Master_Slave

T4_Master_Slave

Reference Clk

1.544 MHz

2.048 MHz

19.44 MHz

38.88 MHz

77.76 MHz

T0_Xsync_In

OCXO

TCXO

T4_Xsync_In

64 KHz

8 KHz

frequencies

10MHz/

20MHz

Serial/Parallel Bus

Offset Monitor

Ref Selector

are

Frequency

T0 Active

Activity &

T4 Active

Interface

Cross-couple data

Figure 1: Functional Block Diagram

automatically

Data Sheet #: TM084

STC4130

Detector

Phase

Control & Status

Registers

Features

•

Digital

Filter

For SDH SETS and SSU

For SONET Stratum 3E, 3, 4E, 4 and SMC

Complies with ITU-T G.812 Type III , G.813, Tel-

cordia GR1244, and GR253

Supports Master/Slave operation with the

SyncLink

slave redundant applications

Accepts 12 individual clock reference inputs

Reference clock inputs are automatically fre-

quency detected

Supports manual or automatic reference selec-

tion

T0 and T4 have independent reference lists and

priority tables for automatic reference selection

8 synchronized output clocks

Output/input phase skew is adjustable in slave

mode, in 0.1nS steps up to 200nS

Hit-less reference and master/slave switching

Phase rebuild on re-lock and reference switches

Better than 0.1 ppb holdover accuracy

Programmable bandwidth, from 90mHz to 107Hz,

for both T0 and T4 DPLL

Supports SPI or parallel bus interface

IEEE 1149.1 JTAG boundary scan

Available in TQ100 ROHS package

IEE 1194.1

Page 1 of 44

JTAG

Synchronous Clock for SETS

Generator

Clock

cross-couple data link for master/

Specifications subject to change without notice

Functional Specification

Rev: P02

19.44/38.88/77.76 MHz

T4_Xsync_Out

19.44/38.88/77.76 MHz

1.544/3.088/6.176/12.352/24.704 MHz

2.048/4.096/8.192/16.384/32.768 MHZ

1.544 MHz/2.048 MHz

8 KHz

2 KHz

T0_Xsync_Out

LVDS 155.52 MHz

44.736 MHz/34.368 MHz

STC4130

Data Sheet

Date: 12/5/06

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