STC4130-I ETC2 [List of Unclassifed Manufacturers], STC4130-I Datasheet - Page 26

• Manufacturer Part Number: STC4130-I
• Description: Synchronous Clock for SETS
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Register Descriptions and Operation
General Register Operation
The STC4130 device has 1, 2, and 4 byte registers. One byte registers are read and written directly. Two and
four byte registers must be read and written in a specific manner and order, as follows:
Multibyte register reads
A multibyte register read must commence with a read of the least significant byte first. This triggers a transfer
of the remaining byte(s) to a holding resgister, ensuring that the remaining data will not change with the con-
tinuing operation of the device. The remaining byte(s) may then be read in any order, and with no timing restric-
tions.
Multibyte register writes
A multibyte register write must commence with a write to the least significant byte first. Subsequent writes to
the remaining byte(s)must be performed in ascending byte order, but with no timing restrictions. Multibyte reg-
ister writes are temporarily stored in a holding register, and are transferred to the target register when the most
significant byte is written.
Clearing bits in the Interrupt Status Register
Interrupt event register (Intr_Event, 0x5e~0x5f) bits are cleared by writing a “1” to the bit position to be
cleared. Interrupt bit positions to be left as is are written with a “0”.
Default Register Settings
Chip_ID, 0x00 (R)
Chip_Rev, 0x02 (R)
Chip_Sub_Rev, 0x03 (R)
Address
Address
Address
0x00
0x01
0x02
0x03
Bit7
Bit7
Bit7
© Copyright 2006 The Connor-Winfield Corp.
Bit6
Bit6
Bit6
Data Sheet #: TM084
Bit5
Bit5
Bit5
Bit4
Bit4
Bit4
All Rights Reserved
0x30
0x41
0x01
0x01
Page 26 of 44
Bit3
Bit3
Bit3
Synchronous Clock for SETS
Specifications subject to change without notice
Bit2
Bit2
Bit2
Rev: P02
STC4130
Data Sheet
Bit1
Bit1
Bit1
Date: 12/5/06
Bit0
Bit0
Bit0