STC4130-I ETC2 [List of Unclassifed Manufacturers], STC4130-I Datasheet - Page 29

• Manufacturer Part Number: STC4130-I
• Description: Synchronous Clock for SETS
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Qualification_Range, 0x12 (R/W)
Reference qualification range, from 0 to +102.3 ppm, in 0.1 ppm steps.
Default value: 100.
Qualification_Timer, 0x14 (R/W)
Reference qualification timer, from 0 to 255 S.
Default value: 10.
Ref_Selector, 0x15 (R/W)
Determines which reference data is displayed in register 0x16 and 0x17. Valid values from 1 to 12.
Default value: 1.
Ref_Frq_Offset, 0x16 (R)
Displays the frequency offset and reference frequency for the reference selected by the Ref_Selector (0x15)
register. Frequency offset is from -204.8 to +204.7 ppm in 0.1 ppm steps, two’s complement. The reference fre-
quency is determined as follows:
Refs_Activity, 0x18 (R)
Address
Address
Address
Address
Address
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
Not used
Ref 8
Bit7
Bit7
Bit7
Bit7
Bit7
Not used
© Copyright 2006 The Connor-Winfield Corp.
Ref 7
Bit6
Bit6
Bit6
Bit6
Bit6
Not used
Reference frequency
T4_Xsync_In T0_Xsync_In
Not used
Data Sheet #: TM084
0x13, bits 6 ~ 4
Ref 6
Bit5
Bit5
Bit5
Bit5
Bit5
000
001
010
100
101
011
110
111
Lower 8 bits of frequency offset
Ref 5
Bit4
Bit4
Bit4
Bit4
Bit4
Lower 8 bits
0 ~ 63 S
Frequency
1.544 MHz
2.048 MHz
19.44 MHz
38.88 MHz
77.76 MHz
All Rights Reserved
No signal
64 KHz
8 KHz
Page 29 of 44
Ref 12
Ref 4
Bit3
Bit3
Bit3
Bit3
Bit3
Synchronous Clock for SETS
Upper 4 bits of frequency offset
Specifications subject to change without notice
Ref 11
Ref 3
Bit2
Bit2
Bit2
Bit2
Bit2
1 ~ 12 (0x1 ~ 0xc)
Rev: P02
Upper 3 bits
STC4130
Ref 10
Ref 2
Data Sheet
Bit1
Bit1
Bit1
Bit1
Bit1
Date: 12/5/06
Ref 1
Ref 9
Bit0
Bit0
Bit0
Bit0
Bit0