STTS424E02BDA3E STMICROELECTRONICS [STMicroelectronics], STTS424E02BDA3E Datasheet - Page 28

• Manufacturer Part Number: STTS424E02BDA3E
• Description: Memory module temperature sensor with a 2 Kb SPD EEPROM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

SPD EEPROM operation
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SPD EEPROM operation
2 Kb SPD EEPROM operation
The 2 Kbit serial EEPROM is able to lock permanently the data in its first half (from location
00h to 7Fh). This facility has been designed specifically for use in DRAM DIMMs (Dual in
line Memory Modules) with Serial Presence Detect. All the information concerning the
DRAM module configuration (such as its access speed, its size, its organization) can be
kept write protected in the first half of the memory.
The first half of the memory area can be write-protected using two different software write
protection mechanisms. By sending the device a specific sequence, the first 128 bytes of
the memory become write protected: permanently or resetable.
These I
organized as 256x8 bits.
I
The device carries a built-in 4-bit Device Type Identifier code (1010) in accordance with the
I
(0110) to define the protection. These codes are used together with the voltage level applied
on the three chip enable inputs (A2, A1, A0). These input signals are used to set the value
that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Device
Select Code. In the end application, A0, A1 and A2 must be directly (not through a pull-up or
pull-down resistor) connected to V
these inputs are not connected, an internal pull-down circuitry makes (A0,A1,A2) = (0,0,0).
The A0 input is used to detect the V
(refer to
The device behaves as a slave device in the I
synchronized by the serial clock. Read and Write operations are initiated by a START
condition, generated by the bus master. The START condition is followed by a Device Select
Code and RW bit (as described in
acknowledge bit.
When writing data to the memory, the memory inserts an acknowledge bit during the 9
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a STOP condition after an Ack for WRITE, and after a NoAck for READ.
Internal device reset - SPD EEPROM
In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR)
circuit is included.
At Power-up (phase during which V
device will not respond to any instruction until V
threshold voltage (this threshold is lower than the minimum V
Table 2: AC SMBus and I
threshold, the device is reset.
2
2
C uses a two wire serial interface, comprising a bi-directional data line and a clock line.
C bus definition to access the memory area and a second Device Type Identifier Code
2
Table 20: Device select
C-compatible electrically erasable programmable memory (EEPROM) devices are
2
C compatibility
code).
DD
Table 20: Device select
DD
HV
or V
is lower than V
voltage, when decoding an SWP or CWP instruction
SS
timings). Once V
to establish the Device Select Code. When
2
C protocol, with all memory operations
DD
has reached the Power On Reset
DD
min but increases continuously), the
code), terminated by an
DD
DD
has passed the POR
operating voltage defined in
STTS424E02
th
bit