STTS424E02BDA3E STMICROELECTRONICS [STMicroelectronics], STTS424E02BDA3E Datasheet - Page 33
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STTS424E02BDA3E
Manufacturer Part Number
STTS424E02BDA3E
Description
Memory module temperature sensor with a 2 Kb SPD EEPROM
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.STTS424E02BDA3E.pdf
(51 pages)
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STTS424E02
5.5.3
Figure 13. Write cycle polling flowchart using ACK
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (t
shown
make use of this, a polling sequence can be used by the bus master.
The sequence, as shown in
●
●
●
First byte of instruction
with RW = 0 already
decoded by the device
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition followed by a Device Select Code (the
first byte of the new instruction).
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
inTable 2: AC SMBus and I
ReSTART
STOP
NO
NO
Figure
START Condition
DEVICE SELECT
WRITE Cycle
Addressing the
with RW = 0
Operation is
in Progress
Returned
Memory
2
ACK
Next
C compatibility timings
13, is:
YES
WRITE Operation
WRITE Operation
DATA for the
Continue the
YES
NO
and Receive ACK
Send Address
Condition
START
, but the typical time is shorter. To
Random READ Operation
SPD EEPROM operation
DEVICE SELECT
Continue the
with RW = 1
YES
AI01847C
w
) is
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