AT90PWM216-16SE ATMEL [ATMEL Corporation], AT90PWM216-16SE Datasheet - Page 131

• Manufacturer Part Number: AT90PWM216-16SE
• Description: 8-bit Microcontroller with 16K Bytes In-System Programmable flash
• Manufacturer: ATMEL [ATMEL Corporation]

16. Power Stage Controller – (PSC0, PSC1 & PSC2)
16.1
16.2
7710D–AVR–08/09
Features
Overview
The Power Stage Controller is a high performance waveform controller.
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Many register and bit references in this section are written in general form.
The purpose of a Power Stage Controller (PSC) is to control power modules on a board. It has
two outputs on PSC0 and PSC1 and four outputs on PSC2.
These outputs can be used in various ways:
Each PSC has two inputs the purpose of which is to provide means to act directly on the gener-
ated waveforms:
The PSC can be chained and synchronized to provide a configuration to drive three half bridges.
Thanks to this feature it is possible to generate a three phase waveforms for applications such
as Asynchronous or BLDC motor drive.
• A lower case “n” replaces the PSC number, in this case 0, 1 or 2. However, when using the
• A lower case “x” replaces the PSC part , in this case A or B. However, when using the register
• “Two Ouputs” to drive a half bridge (lighting, DC motor ...)
• “One Output” to drive single power transistor (DC/DC converter, PFC, DC motor ...)
• “Four Outputs” in the case of PSC2 to drive a full bridge (lighting, DC motor ...)
• Current sensing regulation
• Zero crossing retriggering
• Demagnetization retriggering
• Fault input
PWM waveform generation function (2 complementary programmable outputs)
Dead time control
Standard mode up to 12 bit resolution
Frequency Resolution Enhancement Mode (12 + 4 bits)
Frequency up to 64 Mhz
Conditional Waveform on External Events (Zero Crossing, Current Sensing ...)
All on chip PSC synchronization
ADC synchronization
Overload protection function
Abnormality protection function, emergency input to force all outputs to high impedance or in
inactive state (fuse configurable)
Center aligned and edge aligned modes synchronization
Fast emergency stop by hardware
register or bit defines in a program, the precise form must be used, i.e., PSOC1 for accessing
PSC 0 Synchro and Output Configuration register and so on.
or bit defines in a program, the precise form must be used, i.e., PFRCnA for accessing PSC n
Fault/Retrigger n A Control register and so on.
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