AT90PWM216-16SE ATMEL [ATMEL Corporation], AT90PWM216-16SE Datasheet - Page 171

• Manufacturer Part Number: AT90PWM216-16SE
• Description: 8-bit Microcontroller with 16K Bytes In-System Programmable flash
• Manufacturer: ATMEL [ATMEL Corporation]

16.25.17 PSC 1 Input Capture Register – PICR1H and PICR1L
16.25.18 PSC 2 Input Capture Register – PICR2H and PICR2L
16.26 PSC2 Specific Register
16.26.1
7710D–AVR–08/09
PSC 2 Output Matrix – POM2
• Bit 7 – PCSTn : PSC Capture Software Trig bit
Set this bit to trigger off a capture of the PSC counter. When reading, if this bit is set it means
that the capture operation was triggered by PCSTn setting otherwise it means that the capture
operation was triggered by a PSC input.
The Input Capture is updated with the PSC counter value each time an event occurs on the
enabled PSC input pin (or optionally on the Analog Comparator output) if the capture function is
enabled (bit PCAEnx in PFRCnx register is set).
The Input Capture Register is 12-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit or
12-bit registers.
Bit
Read/Write
Initial Value
• Bit 7 – POMV2B3: Output Matrix Output B Ramp 3
This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 3
• Bit 6 – POMV2B2: Output Matrix Output B Ramp 2
This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 2
• Bit 5 – POMV2B1: Output Matrix Output B Ramp 1
This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 1
• Bit 4 – POMV2B0: Output Matrix Output B Ramp 0
This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 0
• Bit 3 – POMV2A3: Output Matrix Output A Ramp 3
This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 3
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
POMV2B3
PCST1
PCST2
R/W
R
R
7
0
7
0
7
0
POMV2B2
R/W
R
R
6
–
0
6
–
0
6
0
POMV2B1
R/W
R
R
5
–
0
5
–
0
5
0
POMV2B0
R/W
R
R
4
–
0
4
–
0
4
0
PICR1[7:0]
PICR2[7:0]
POMV2A3
R/W
R
R
3
0
3
0
3
0
POMV2A2
AT90PWM216/316
R/W
R
R
2
0
2
0
2
0
PICR1[11:8]
PICR2[11:8]
POMV2A1
R/W
R
R
1
0
1
0
1
0
POMV2A0
R/W
R
R
0
0
0
0
0
0
PICR1H
PICR1L
PICR2H
PICR2L
POM2
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