AT90PWM216-16SE ATMEL [ATMEL Corporation], AT90PWM216-16SE Datasheet - Page 199

• Manufacturer Part Number: AT90PWM216-16SE
• Description: 8-bit Microcontroller with 16K Bytes In-System Programmable flash
• Manufacturer: ATMEL [ATMEL Corporation]

18.8
18.8.1
7710D–AVR–08/09
Asynchronous Data Reception
Asynchronous Clock Recovery
Note:
The USART includes a clock recovery and a data recovery unit for handling asynchronous data
reception. The clock recovery logic is used for synchronizing the internally generated baud rate
clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic sam-
ples and low pass filters each incoming bit, thereby improving the noise immunity of the
Receiver. The asynchronous reception operational range depends on the accuracy of the inter-
nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.
The clock recovery logic synchronizes internal clock to the incoming serial frames.
illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times
the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The hor-
izontal arrows illustrate the synchronization variation due to the sampling process. Note the
larger time variation when using the Double Speed mode (U2X = 1) of operation. Samples
denoted zero are samples done when the RxD line is idle (i.e., no communication activity).
Figure 18-6. Start Bit Sampling
When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the
start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in
the figure. The clock recovery logic then uses samples 8, 9, and 10 for Normal mode, and sam-
Assembly Code Example
C Code Example
TABLE 2.
USART_Flush:
void USART_Flush( void )
{
}
sbis UCSRA, RXC0
ret
lds
rjmp USART_Flush
unsigned char dummy;
while ( UCSRA & (1<<RXC0) ) dummy = UDR;
1. The example code assumes that the part specific header file is included.
(U2Xn = 0)
(U2Xn = 1)
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
Sample
Sample
RxDn
r16, UDR
(1)
0
0
IDLE
0
(1)
1
1
2
3
2
4
5
3
6
7
4
8
START
9
5
10
AT90PWM216/316
11
6
12
13
7
14
15
8
16
1
1
Figure 18-6
2
BIT 0
3
2
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