LPC2132FBD64/01 NXP [NXP Semiconductors], LPC2132FBD64/01 Datasheet - Page 29

• Manufacturer Part Number: LPC2132FBD64/01
• Description: Single-chip 16/32-bit microcontrollers; 32/64/128/256/512 kB ISP/IAP flash with 10-bit ADC and DAC
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
[4]
[5]
[6]
[7]
[8]
[9]
[10] On pin VBAT.
[11] Optimized for low battery consumption.
[12] The input threshold voltage of I
[13] To V
Table 7.
V
[1]
[2]
[3]
[4]
[5]
[6]
LPC2131_32_34_36_38_4
Product data sheet
Symbol
V
C
E
E
E
E
E
DDA
IA
D
L(adj)
O
G
T
ia
V
3-state outputs go into 3-state mode when V
Accounts for 100 mV voltage drop in all supply lines.
Only allowed for a short time period.
Minimum condition for V
Applies to P1.16 to P1.25.
logic 0 while an input voltage above 3.0 V will be recognized as a logic 1.
The ADC is monotonic, there are no missing codes.
The differential linearity error (E
The integral no-linearity (E
appropriate adjustment of gain and offset errors. See
The offset error (E
ideal curve. See
The gain error (E
error, and the straight line which fits the ideal transfer curve. See
The absolute voltage error (E
non-calibrated A/D and the ideal transfer curve. See
= 2.5 V to 3.6 V; T
DD
SS
supply voltages must be present.
.
ADC static characteristics
Parameter
analog input voltage
analog input
capacitance
differential linearity error V
integral non-linearity
offset error
gain error
absolute error
Figure
G
O
) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
amb
7.
I
= 4.5 V, maximum condition for V
= 40 C to +85 C, unless otherwise specified; ADC frequency 4.5 MHz.
L(adj)
T
) is the maximum difference between the center of the steps of the actual transfer curve of the
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
2
D
C-bus pins meets the I
) is the difference between the actual step width and the ideal step width. See
Conditions
V
V
V
V
SSA
SSA
SSA
SSA
SSA
DD
= 0 V, V
= 0 V, V
= 0 V, V
= 0 V, V
= 0 V, V
is grounded.
Rev. 04 — 16 October 2007
Figure
Figure
2
C-bus specification, so an input voltage below 1.5 V will be recognized as a
DDA
DDA
DDA
DDA
DDA
I
= 5.5 V.
7.
= 3.3 V
= 3.3 V
= 3.3 V
= 3.3 V
= 3.3 V
7.
Figure
7.
[1][2]
[3]
[4]
[5]
[6]
LPC2131/32/34/36/38
Min
0
-
-
-
-
-
-
Single-chip 16/32-bit microcontrollers
Typ
-
-
-
-
-
-
-
Figure
Max
V
1
© NXP B.V. 2007. All rights reserved.
1
2
3
0.5
4
DDA
7.
Unit
V
pF
LSB
LSB
LSB
%
LSB
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