LPC2880FET180 PHILIPS [NXP Semiconductors], LPC2880FET180 Datasheet - Page 15

• Manufacturer Part Number: LPC2880FET180
• Description: 16/32-bit ARM microcontrollers; 8 kB cache, up to 1 MB flash, Hi-Speed USB 2.0 device, and SDRAM memory interface
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
LPC2880_LPC2888_1
Preliminary data sheet
6.3.1 Cache operation
6.3.2 Features
6.3 Cache
6.4 Flash memory and programming
The CPU of the LPC2880/LPC2888 has been extended with a 2-way set-associative
cache controller. The cache is 8 kB in size and can store both data and instruction code.
If code that is being executed is present in the cache from a previous execution, the CPU
will not experience code fetch waits. Similarly, if requested data is present in the cache,
the CPU will not experience a data access wait.
The trade-off of introducing this cache is that each AHB access that bypasses the cache
will have an extra wait state inserted. Therefore it is advisable to enable instruction
caching (and preferably data caching as well) for all memories, to provide the highest
performance.
This cache works as follows, for each page of which the cache is enabled:
The cache can be set to data-only, instruction-only or combined (unified) caching. The
cache has 16 configurable pages, each 2 MB in range. The pages occupy the bottom
32 MB of the memory map. The virtual address and enable/disable status is configurable
for each page.
The LPC2888 incorporates 1 MB flash memory system, while the LPC2880 is a flash-less
device. The flash memory of the LPC2888 may be used for both code and data storage.
Programming of the flash memory may be accomplished in several ways. It may be
programmed In System via the USB port. The application program may also erase and/or
program the flash while the application is running, allowing a great degree of flexibility for
data storage, field firmware upgrades, etc.
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If a read is requested and the information is not in the cache (a cache miss), a line of
eight 32-bit words will be read from the AHB bus. The CPU waits until this process is
complete.
If a read is requested and the information is found in the cache (a cache hit), the
information is read from cache, with zero wait states.
If data is written, and the location is not in the cache (a cache miss), the data will be
written directly to memory.
If data is written, and the location is in the cache, because this location has been read
before (a cache hit), then data is written into the cache with zero wait states and the
cache line is marked as ‘dirty’.
If a ‘dirty’ cache line is about to be discarded because of a cache miss on a read
request, this line will first be written back to memory (a cache-line flush).
8 kB, 2-way set-associative cache.
May be used as both an instruction and data cache.
Zero wait states for a cache hit.
16 configurable pages, each 2 MB in range.
16/32-bit ARM microcontrollers with external memory interface
Rev. 01 — 22 June 2006
LPC2880; LPC2888
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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