ST7FLITE02 STMICROELECTRONICS [STMicroelectronics], ST7FLITE02 Datasheet - Page 28

• Manufacturer Part Number: ST7FLITE02
• Description: 8-BIT MICROCONTROLLER WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST7LITE0x, ST7LITESx
7.4 RESET SEQUENCE MANAGER (RSM)
7.4.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in
■
■
■
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in
■
■
■
Figure 15.Reset Block Diagram
28/125
1
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
Active Phase depending on the RESET source
256 CPU clock cycle delay
RESET vector fetch
Note 1: See “Illegal Opcode Reset” on page 79. for more details on illegal opcode reset conditions.
RESET
section 11.2.1 on page 54
Figure
14:
V
Figure
DD
R
ON
for further details.
15:
FILTER
GENERATOR
PULSE
The 256 CPU clock cycle delay allows the oscilla-
tor to stabilise and ensures that recovery has tak-
en place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
If the PLL is enabled by option byte, it outputs the
clock after an additional delay of t
Figure
Figure 14. RESET Sequence Phases
Active Phase
12).
WATCHDOG RESET
ILLEGAL OPCODE RESET
LVD RESET
256 CLOCK CYCLES
INTERNAL RESET
RESET
INTERNAL
RESET
STARTUP
VECTOR
FETCH
1)
(see