MC908JL16CFAE FREESCALE [Freescale Semiconductor, Inc], MC908JL16CFAE Datasheet - Page 125

• Manufacturer Part Number: MC908JL16CFAE
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

9.3.1 Clock Select and Divide Circuit
The clock select and divide circuit selects one of three clock sources and divides it by a configurable value
to generate the input clock to the converter (ADCK). The clock can be selected from one of the following
sources:
Whichever clock is selected, its frequency must fall within the acceptable frequency range for ADCK. If
the available clocks are too slow, the ADC10 will not perform according to specifications. If the available
clocks are too fast, then the clock must be divided to the appropriate frequency. This divider is specified
by the ADIV[1:0] bits and can be divide-by 1, 2, 4, or 8.
9.3.2 Input Select and Pin Control
Only one analog input may be used for conversion at any given time. The channel select bits in ADCSC
are used to select the input signal for conversion.
9.3.3 Conversion Control
Conversions can be performed in either 10-bit mode or 8-bit mode as determined by the MODE bits.
Conversions can be initiated by either a software or hardware trigger. In addition, the ADC10 module can
be configured for low power operation, long sample time, and continuous conversion.
9.3.3.1 Initiating Conversions
A conversion is initiated:
If continuous conversions are enabled a new conversion is automatically initiated after the completion of
the current conversion. In software triggered operation, continuous conversions begin after ADCSC is
written and continue until aborted. In hardware triggered operation, continuous conversions begin after a
hardware trigger event and continue until aborted.
9.3.3.2 Completing Conversions
A conversion is completed when the result of the conversion is transferred into the data result registers,
ADRH and ADRL. This is indicated by the setting of the COCO bit. An interrupt is generated if AIEN is
high at the time that COCO is set.
Freescale Semiconductor
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The asynchronous clock source (ACLK) — This clock source is generated from a dedicated clock
source which is enabled when the ADC10 is converting and the clock source is selected by setting
the ACLKEN bit. When the ADLPC bit is clear, this clock operates from 1–2 MHz; when ADLPC is
set it operates at 0.5–1 MHz. This clock is not disabled in STOP and allows conversions in stop
mode for lower noise operation.
Alternate Clock Source — This clock source is equal to the external oscillator clock or a four times
the bus clock. The alternate clock source is MCU specific, see
availability of this clock source option. This clock is selected when ADICLK and ACLKEN are both
low.
The bus clock — This clock source is equal to the bus frequency. This clock is selected when
ADICLK is high and ACLKEN is low.
Following a write to ADCSC (with ADCH bits not all 1s) if software triggered operation is selected.
Following a hardware trigger event if hardware triggered operation is selected.
Following the transfer of the result to the data registers when continuous conversion is enabled.
MC68HC908JL16 Data Sheet, Rev. 1.1
Table 9-1
to determine source and
Functional Description
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