MC908JL16CFAE FREESCALE [Freescale Semiconductor, Inc], MC908JL16CFAE Datasheet - Page 206

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MC908JL16CFAE

Manufacturer Part Number
MC908JL16CFAE
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Electrical Specifications
17.6 5-V Control Timing
206
Low-voltage inhibit, trip falling voltage
Low-voltage inhibit, trip rising voltage
Low-voltage inhibit reset/recovery hysteresis
Internal operating frequency
RST input pulse width low
TIM2 external clock input
IRQ interrupt pulse width low (edge-triggered)
IRQ interrupt pulse period
1. V
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I
4. Wait I
5. Stop I
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum V
8. R
1. V
2. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
3. Values are based on characterization results, not tested in production.
4. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 t
Less than 100 pF on all outputs. C
run I
100 pF on all outputs. C
V
noted.
DD
DD
DD
PU
= 4.5 to 5.5 Vdc, V
DD
is reached.
is measured at V
= 4.5 to 5.5 Vdc, V
DD
DD
. Measured with all modules enabled.
measured using external square wave clock source (f
measured with OSC1 grounded; no port pins sourcing current.
DD
is not reached before the internal POR reset is released, RST must be driven low externally until minimum
DD
Characteristic
RST
IRQ
measured using external square wave clock source (f
DD
Characteristic
(2)
(3)
SS
SS
L
= 5.0V.
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait I
= 0 Vdc, T
= 0 Vdc, T
Table 17-4. DC Electrical Characteristics (5V)
(1)
L
A
A
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
Figure 17-1. RST and IRQ Timing
(1)
= T
= T
Table 17-5. Control Timing (5V)
MC68HC908JL16 Data Sheet, Rev. 1.1
L
L
(3)
to T
to T
t
H
H
t
ILIH
RL
, unless otherwise noted.
; timing shown with respect to 20% V
t
ILIL
Symbol
V
OP
V
V
TRIPR
TRIPF
HYS
= 8MHz). All inputs 0.2V from rail. No dc loads. Less than
Symbol
f
T2CLK
t
t
OP
t
f
ILIH
IRL
ILIL
OP
= 8MHz). All inputs 0.2V from rail. No dc loads.
3.90
4.00
Min
Note
Min
DD
750
100
(4)
and 70% V
Typ
4.20
4.30
100
(2)
Freescale Semiconductor
CYC
Max
SS
8
4
, unless otherwise
.
Max
4.50
4.60
MHz
MHz
Unit
t
CYC
ns
ns
DD
Unit
mV
.
V
V

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