MC9S12E32CFU FREESCALE [Freescale Semiconductor, Inc], MC9S12E32CFU Datasheet - Page 376

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MC9S12E32CFU

Manufacturer Part Number
MC9S12E32CFU
Description
HCS12 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
11.4.7.4
Initialize all registers and set the LDOK bit before setting the PWMEN bit. With LDOK set, setting
PWMEN for the first time after reset, immediately loads the PWM generator thereby setting the PWMRF
flag. PWMRF generates a CPU interrupt request if the PWMRIE bit is set. In complementary channel
operation with current-status correction selected, PWM value registers one, three, and five control the
outputs for the first PWM cycle.
Setting PWMEN for the first time after reset without first setting LDOK loads a prescaler divisor of one,
a PWM value of $0000, and an unknown modulus. The PWM generator uses the last values loaded if
PWMEN is cleared and then set while LDOK equals zero.Initializing the deadtime register, after setting
PWMEN or OUTCTLx, can cause an improper deadtime insertion. However, the deadtime can never be
shorter than the specified value.
376
PWMEN
PWMEN
CLOCK
CLOCK
IPBus
IPBus
PWM
PWM
PINS
PINS
BIT
BIT
Initialization
Even if LDOK is not set, setting PWMEN also sets the PWMRF flag. To
prevent a CPU interrupt request, clear the PWMRIE bit before setting
PWMEN.
HI-Z
Figure 11-75. PWMEN and PWM Pins in Complementary Operation
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Figure 11-74. PWMEN and PWM Pins in Independent Operation
PWM VALUE = 2
MODULUS = 3
COUNTER
PWMRF = 1
LDOK = 1
Up-Only
MC9S12E128 Data Sheet, Rev. 1.07
PWM
Figure 11-73. Untitled Figure
LDFQ[3:0] = 00 = Reload every cycle
NOTE
1
4
2
1
ACTIVE
ACTIVE
1
2
2
1
0
1
2
1
Freescale Semiconductor
HI-Z
HI-Z

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