MC9S12E32CFU FREESCALE [Freescale Semiconductor, Inc], MC9S12E32CFU Datasheet - Page 510

• Manufacturer Part Number: MC9S12E32CFU
• Description: HCS12 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Chapter 17 Interrupt (INTV1)
17.5
The INT supports three system reset exception request types: normal system reset or power-on-reset
request, crystal monitor reset request, and COP watchdog reset request. The type of reset exception request
must be decoded by the system and the proper request made to the core. The INT will then provide the
service routine address for the type of reset requested.
17.6
As shown in the block diagram in
and control, an optional highest priority I interrupt (HPRIO) block, and a priority decoder to evaluate
whether pending interrupts are valid and assess their priority.
17.6.1
The INT registers are accessible only in special modes of operation and function as described in
Section 17.3.2.1, “Interrupt Test Control
previously.
17.6.2
When the optional HPRIO block is implemented, the user is allowed to promote a single I-bit maskable
interrupt to be the highest priority I interrupt. The HPRIO evaluates all interrupt exception requests and
passes the HPRIO vector to the priority decoder if the highest priority I interrupt is active. RTI replaces
the promoted interrupt source.
17.6.3
The priority decoder evaluates all interrupts pending and determines their validity and priority. When the
CPU requests an interrupt vector, the decoder will provide the vector for the highest priority interrupt
request. Because the vector is not supplied until the CPU requests it, it is possible that a higher priority
interrupt request could override the original exception that caused the CPU to request the vector. In this
case, the CPU will receive the highest priority vector and the system will process this exception instead of
the original request.
If for any reason the interrupt source is unknown (e.g., an interrupt request becomes inactive after the
interrupt has been recognized but prior to the vector request), the vector address will default to that of the
last valid interrupt that existed during the particular interrupt sequence. If the CPU requests an interrupt
vector when there has never been a pending interrupt request, the INT will provide the software interrupt
(SWI) vector address.
510
Resets
Interrupts
Interrupt Registers
Highest Priority I-Bit Maskable Interrupt
Interrupt Priority Decoder
Care must be taken to ensure that all exception requests remain active until
the system begins execution of the applicable service routine; otherwise, the
exception request may not be processed.
Figure
MC9S12E128 Data Sheet, Rev. 1.07
17-1, the INT contains a register block to provide interrupt status
Register,” and
NOTE
Section 17.3.2.2, “Interrupt Test
Freescale Semiconductor
Registers,”