M40Z300MH STMICROELECTRONICS [STMicroelectronics], M40Z300MH Datasheet - Page 4
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M40Z300MH
Manufacturer Part Number
M40Z300MH
Description
NVRAM CONTROLLER for up to EIGHT LPSRAM
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.M40Z300MH.pdf
(16 pages)
Available stocks
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Part Number
Manufacturer
Quantity
Price
M40Z300, M40Z300W
Table 3. Truth Table
Table 4. AC Measurement Conditions
DATA RETENTION LIFETIME CALCULATION
Most low power SRAMs on the market today can
be used with the M40Z300/W NVRAM Controller.
There are, however some criteria which should be
used in making the final choice of which SRAM to
use. The SRAM must be designed in a way where
the chip enable input disables all other inputs to
the SRAM. This allows inputs to the M40Z300/W
and SRAMs to be Don’t Care once V
V
data retention down to V
able access time must be sufficient to meet the
system needs with the chip enable propagation
delays included. If the SRAM includes a second
Chip Enable pin (E2), this pin should be tied to
V
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0V. Manufacturers gen-
erally specify a typical condition for room temper-
ature along with a worst case condition (generally
at elevated temperatures). The system level re-
quirements will determine the choice of which val-
ue to use. The data retention current value of the
SRAMs can then be added to the I
4/16
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
PFD
OUT
.
(min). The SRAM should also guarantee
E
H
L
L
L
L
Inputs
B
X
H
H
L
L
CC
= 2.0V. The chip en-
CCDR
CC
A
H
H
X
L
L
falls below
0 to 3V
1.5V
value of
5ns
E1
H
H
H
H
CON
L
Figure 3. AC Testing Load Circuit
the M40Z300/W to determine the total current re-
quirements for data retention. The available bat-
tery capacity for the SNAPHAT of your choice can
then be divided by this current to determine the
amount of data retention available (see Table 8).
CAUTION: Take care to avoid inadvertent dis-
charge through V
tery has been attached.
For a further more detailed review of lifetime cal-
culations, please see Application Note AN1012.
C L includes JIG capacitance
DEVICE
UNDER
TEST
E2
H
H
H
H
CON
L
Outputs
OUT
and E1
C L = 50pF
E3
333
H
H
H
H
CON
L
CON
-E4
CON
E4
after bat-
AI02393
H
H
H
H
CON
L
1.73V