LM79 NSC [National Semiconductor], LM79 Datasheet - Page 22

• Manufacturer Part Number: LM79
• Description: Microprocessor System Hardware Monitor
• Manufacturer: NSC [National Semiconductor]

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Functional Description
All Interrupts are indicated in the two Interrupt Status Reg-
isters. The NMI/IRQ and SMI outputs have individual mask
registers, and individual masks for each Interrupt. As de-
scribed in Section 3.3, these two hardware Interrupt lines
can also be enabled/disabled in the Configuration Register.
The Configuration Register is also used to set the mode of
the NMI/IRQ Interrupt line.
8.1 Interrupt Clearing
Reading the Interrupt Status Register will output the con-
tents of the Register, and reset the Register. A subsequent
read done before the analog “round-robin” monitoring loop is
complete will indicate a cleared Register. Allow at least 1.5
seconds to allow all Registers to be updated between reads.
In summary, the Interrupt Status Register clears upon being
read, and requires at least 1.5 seconds to be updated. When
the Interrupt Status Register clears, the hardware interrupt
line will also clear until the Registers are updated by the
monitoring loop.
The hardware Interrupt lines are cleared with the INT__Clear
bit, which is Bit 3 of the Configuration Register. When this bit
is high, the LM79 monitoring loop will stop. It will resume
when the bit is low.
9.0 RESET AND Power Switch Bypass OUTPUTS
In PC applications the open drain Power Switch Bypass
provides a gate drive signal to an external P-channel MOS-
FET power switch. This external MOSFET then would keep
power turned on regardless of the state of front panel power
switches when software power control is used. In any given
application this signal is not limited to the function described
by its label. For example, since the LM79 incorporates tem-
perature sensing, the Power Switch Bypass output could
also be utilized to control power to a cooling fan. Take Power
Switch Bypass active low by setting Bit 6 in the Configuration
Register high.
RESET is intended to provide a master reset to devices
connected to this line. SMI Mask Register 2, Bit 7, must be
set high to enable this function. Setting Bit 4 in the Configu-
ration Register high outputs a least 20 ms low on this line, at
the end of which Bit 4 in the Configuration Register automati-
cally clears. Again, the label for this pin is only its suggested
use. In applications where the RESET capability is not
needed it can be used for any type of digital control that
requires a 20 ms active low open drain output.
• Chassis Intrusion: This is an active high interrupt from
• SMI__IN:
any type of device that detects and captures chassis
intrusion violations. This could be accomplished me-
chanically, optically, or electrically, and circuitry external
to the LM79 is expected to latch the event. The design of
the LM79 allows this input to go high even with no power
applied to the LM79, and no clamping or other interfer-
ence with the line will occur. This line can also be pulled
low for at least 20 ms by the LM79 to reset a typical
Chassis Intrusion circuit. Accomplish this reset by setting
Bit 7 of NMI Mask Register 2 high. The bit in the Register
is self-clearing.
way to chain the SMI Interrupt from other devices through
the LM79 to the processor.
This active low Interrupt merely provides a
(Continued)
22
10.0 POST RAM
The POST RAM is located at address x0h and x4h, which
typical address decoders will decode to 80h or 84h, where
the BIOS will output Power On Self Test codes. A write to the
POST RAM auto-increments the internal pointer of the
LM79. Up to 32 bytes may be stored. An excess of 32 bytes
will generate an Interrupt and stop incrementing.
The POST RAM is read as like any other register at Ports
x5h and x6h, with the POST RAM located at the LM79
Internal Address from 00h to 1Fh. Reading the POST RAM
via x6h will also auto-increment, but this is a separate pointer
than the one used for ports 80h and 84h.
11.0 NAND TREE TESTS
A NAND tree is provided in the LM79 for Automated Test
Equipment (ATE) board level connectivity testing. NAND tree
tests are accomplished after power on reset when the Con-
figuration Register is in reset state, with the Start Bit, Bit 0 of
the Configuration Register low, and the INT__Clear (Bit 3)
high. In this mode, forcing the SMI output low before the first
write to the configuration register takes all pins except Power
Switch Bypass, RESET, -IN5, -IN6, V
to a high impedance (either TRI-STATE or open drain) state.
All high impedance pins can then be taken to 0 and V
accomplish NAND tree tests.
To perform a NAND tree test all pins included in the NAND
tree should be driven to 1. Each individual pin (excluding the
aforementioned exceptions) can be toggled and the resulting
toggle observed on the NTEST pin. Allow for a typical propa-
gation delay of 200 ns.
CC
, GNDA, and GNDD
CC
to