LM79 NSC [National Semiconductor], LM79 Datasheet - Page 4

• Manufacturer Part Number: LM79
• Description: Microprocessor System Hardware Monitor
• Manufacturer: NSC [National Semiconductor]

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Power
Switch
Bypass
FAN3–FAN1
SCL
SDA
RESET
VID4/NTEST
GNDA
−IN6
FB6
FB5
−IN5
IN4–IN0
VID3–VID0
BTI
NMI/IRQ
SMI
A2–A0
CS
TOTAL PINS
Pin Description
Name(s)
Pin
Number
17–19
29–33
34–37
41–43
Pin
16
20
21
22
23
24
25
26
27
28
38
39
40
44
Number
(Continued)
of Pins
44
1
3
1
1
1
1
1
1
1
1
1
5
4
1
1
1
3
1
Digital Output
Digital Input
Digital Input
Digital I/O
Digital Output
Digital
Input/Test
Output
GROUND
Analog Input
Analog Output
Analog Output
Analog Input
Analog Input
Digital Input
Digital Input
Digital Output
Digital Output
Digital Input
Digital Input
Type
An active low open drain output intended to drive an external P-channel
power MOSFET for software power control.
0V to +5V amplitude fan tachometer input.
Serial Bus Clock.
Serial Bus bidirectional Data.
Master Reset, 5 mA driver (open drain), active low output with a 20 ms
minimum pulse width. Available when enabeld via Bit 7 in SMI Mask
Register 2.
By default an input for the VID4 power supply readout for the system
processor (Pentium/PRO). Can be programmed as a NAND Tree
totem-pole output that provides board-level connectivity testing. Refer to
Section 11.0 on NAND Tree testing.
Internally connected to all analog circuitry. The ground reference for all
analog inputs.
Ground-referred inverting op amp input. Refer to Section 4.0 , “ANALOG
INPUTS”.
Output of inverting op amp for Input 6. Refer to Section 4.0 , “ANALOG
INPUTS”.
Output of inverting op amp for Input 5. Refer to Section 4.0 , “ANALOG
INPUTS”.
Ground-referred inverting op amp input. Refer to Section 4.0 , “ANALOG
INPUTS”.
0V to 4.096V FSR Analog Inputs.
Inputs for the power supply readouts for system microprocessor
(Pentium/PRO). This value is read in the VID/Fan Divisor Register.
Board Temperature Interrupt driven by O.S. outputs of additional
temperature sensors such as LM75. Provides internal pull-up of 10 k .
Non-Maskable Interrupt (open source)/Interrupt Request (open drain).
The mode is selected with Bit 5 of the Configuration Register and the
output is enabled when Bit 2 of the Configuration Register is set to 1.
The default state is disabled and IRQ mode.
System Management Interrupt (open drain). This output is enabled when
Bit 1 in the Configuration Register is set to 1. The default state is
disabled.
The three lowest order bits of the 16-bit ISA Address Bus. A0
corresponds to the lowest order bit.
Chip Select input from an external decoder which decodes high order
address bits on the ISA Address Bus. This is an active low input.
4
Description