LM79 NSC [National Semiconductor], LM79 Datasheet - Page 27

• Manufacturer Part Number: LM79
• Description: Microprocessor System Hardware Monitor
• Manufacturer: NSC [National Semiconductor]

Bit
Bit
Bit
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Functional Description
13.7 SMI Mask Register 2 — Address 44h
Power on default
13.8 NMI Mask Register 1 — Address 45h
Power on default
13.9 NMI Mask Register 2 — Address 46h
Power on
IN4
-IN5
-IN6
FAN3
Chassis Intrusion
FIFO Overflow
SMI__IN
RESET Enable
IN0
IN1
IN2
IN3
Temperature
BTI
FAN1
FAN2
IN4
-IN5
-IN6
FAN3
Chassis Intrusion
FIFO Overflow
SMI__IN
Chassis Clear
Name
<
Name
Name
7:0
>
<
<
= 01000000 binary
7:0
7:0
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
>
>
Read/
Write
= 00h
= 00h
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/
Read/
Write
Write
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
(Continued)
A one disables the corresponding interrupt status bit for SMI interrupt.
A one disables the corresponding interrupt status bit for SMI interrupt.
A one disables the corresponding interrupt status bit for SMI interrupt.
A one disables the corresponding interrupt status bit for SMI interrupt.
A one disables the corresponding interrupt status bit for SMI interrupt.
A one disables the corresponding interrupt status bit for SMI interrupt.
A one disables the corresponding interrupt status bit for SMI interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
A one disables the corresponding interrupt status bit for NMI/IRQ interrupt.
Note: The Power on default is 1 for this bit.
A one outputs a minimum 20 ms active low pulse on the Chassis Intrusion pin. The
register bit self clears after the pulse has been output.
<
7
>
= 1 in SM Mask Register 2 enables the RESET in the Configuration Register.
27
Description
Description
Description
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