AK5702VN AKM [Asahi Kasei Microsystems], AK5702VN Datasheet - Page 26

• Manufacturer Part Number: AK5702VN
• Description: 4-Channel ADC with PLL & MIC-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

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A reference clock of PLL is selected among the input clocks to MCKI, BCLK or LRCK pin. The required clock to the
AK5702 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (Table 4).
a) PLL Slave Mode 1 (PLL reference clock: MCKI pin)
BCLK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose not
matter. MCKO pin outputs the frequency selected by PS1-0 bits (Table 9) and the output is enabled by MCKO bit.
Sampling frequency can be selected by FS3-0 bits (Table 5).
The external clocks (MCKI, BCLK and LRCK) should always be present whenever the ADC is in operation (PMADAL
bit = “1” or PMADAR bit = “1” or PMADBL bit = “1” or PMADBR bit = “1”). If these clocks are not provided, the
AK5702 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic
internally. If the external clocks are not present, the ADC should be in the power-down mode (PMADAL= PMADAR =
PMADBL = PMADBR bits = “0”).
b) PLL Slave Mode 2 (PLL reference clock: BCLK or LRCK pin)
Sampling frequency corresponds to 7.35kHz to 48kHz by changing FS3-0 bits (Table 6).
MS0623-E-00
PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
Figure 22. PLL Slave Mode 2 (PLL Reference Clock: LRCK or BCLK pin)
Figure 21. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
AK5702
AK5702
MCKI
MCKO
BCLK
LRCK
SDTOA/B
MCKI
BCLK
LRCK
SDTOA/B
256fs/128fs/64fs/32fs
≥ 32fs
1fs
32fs, 64fs
- 26 -
11.2896MHz, 12MHz, 12.288MHz, 13MHz
13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz
1fs
MCLK
BCLK
LRCK
SDTI
BCLK
LRCK
SDTI
DSP or μP
DSP or μP
[AK5702]
2007/06