AK5702VN AKM [Asahi Kasei Microsystems], AK5702VN Datasheet - Page 48

• Manufacturer Part Number: AK5702VN
• Description: 4-Channel ADC with PLL & MIC-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

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Upon power-up, the AK5702 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset
to their initial values.
The ADC enters an initialization cycle that starts when the PMADAL or PMADAR or PMADBL or PMADBR bit is
changed from “0” to “1”. The initialization cycle time is 3088/fs=70.0ms@fs=44.1kHz when HPF1-0 bits are “00” (Table
37). During the initialization cycle, the ADC digital data outputs of both channels are forced to a 2’s complement, “0”.
The ADC output reflects the analog input signal after the initialization cycle is complete.
MS0623-E-00
HPFA/B1
System Reset
bit
0
0
1
1
1
(Note) The recommendaion values in Table 36 are the shortest cycle time that the offset does not occur. The initial
data of ADC may have some offset by the external condition such as a use of microphone. If this offset isn’t small,
the longer initialization cycle should be selected as ADRSTbit=“0” in order to prevent the offset data. Or, do not
use the initial data of ADC.
HPFA/B0
bit
0
1
0
1
1
INCA/B
bit
0
0
0
0
1
3088/f
1552/f
3088/f
1552/f
784/fs
Cycle
Table 37. ADC Initialization Cycle
s
s
s
s
(Recommendation)
(Recommendation)
fs=44.1kHz
70.0ms
35.2ms
17.8ms
70.0ms
35.2ms
- 48 -
Init Cycle
(Recommendation)
(Recommendation)
fs=22.05kHz
140.0ms
140.0ms
70.4ms
35.6ms
70.4ms
(Recommendation)
fs=11.025kHz
280.1ms
140.8ms
280.1ms
140.8ms
71.1ms
[AK5702]
(default)
2007/06