AK5702VN AKM [Asahi Kasei Microsystems], AK5702VN Datasheet - Page 46
AK5702VN
Manufacturer Part Number
AK5702VN
Description
4-Channel ADC with PLL & MIC-AMP
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet
1.AK5702VN.pdf
(76 pages)
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AK5702VN-L
Manufacturer:
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20 000
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When writing to the IVA/BL7-0 and IVA/BR7-0 bits continuouslly, the control register should be written by an interval
more than zero crossing timeout. If not, IVA/BL and IVA/BR are not changed since zero crossing counter is reset at every
write operation. If the same register value as the previous write operation is written to IVA/BL and IVA/BR, this write
operation is ignored and zero crossing counter is not reset. Therefore, IVA/BL and IVA/BR can be written by an interval
less than zero crossing timeout.
(1) The IVA/BL value becomes the start value if the IVA/BL and IVA/BR are different when the ALC starts. The wait
(2) Writing to IVA/BL and IVA/BR registers (18H and 19H) is ignored during ALC operation. After ALC is disabled,
MS0623-E-00
time from ALC bit = “1” to ALC operation start by IVA/BL7-0 bits is at most recovery time (WTMA/B2-0 bits) plus
zerocross timeout period (ZTMA/B1-0 bits).
the IVOL changes to the last written data by zero crossing or timeout. When ALC is enabled again, ALCA/B bit
should be set to “1” by an interval more than zero crossing timeout period after ALCA/B bit = “0”.
ALCA /B Status
Internal IVA/BL
Internal IVA/BR
ALCA/B bit
IVA/BL7-0 bits
IVA/BR7-0 bits
Figure 44. IVOL value during 2ch ALC operation
C6H(+20dB)
E1H(+30dB)
Disable
(1)
E1(+30dB) --> F1(+36dB)
E1(+30dB) --> F1(+36dB)
- 46 -
E1H(+30dB)
C6H(+20dB)
Enable
(2)
C6H(+20dB)
E1(+30dB)
Disable
[AK5702]
2007/06
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