AK5702VN AKM [Asahi Kasei Microsystems], AK5702VN Datasheet - Page 58

• Manufacturer Part Number: AK5702VN
• Description: 4-Channel ADC with PLL & MIC-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

MS0623-E-00
Addr
Addr
Addr
0CH
0DH
0EH
LMTHA1-0: ALCA Limiter Detection Level / Recovery Counter Reset Level (Table 28)
RGA1-0: ALCA Recovery GAIN Step (Table 32)
LMATA1-0: ALCA Limiter ATT Step (Table 29)
ZELMNA: Zero Crossing Detection Enable at ALCA Limiter Operation
ALCA: ALC Enable
ALC4: All ALCs Link Mode Enable
LFST: ALC Limiter Operation Beyond FS
TE3-0: EXT Master Mode Enable
TMASTER: EXT Master Mode
Default: “00”
Default: “00”
Default: “00”
0: Enable (default)
1: Disable
0: ALCA Disable (default)
1: ALCA Enable
0: Disable (default)
1: All ALCs of 4-channel ADC operate at the same time.
0: At the Individual Zero Crossing Points or at the Zero Crossing Timeout (default)
1: Immediately
When TE3-0 bits is set to “0101”, the write operation to addr=0EH is enabled.
TE3-0 bits should be set to “1010” except for EXT Master Mode.
TE3-0 bits must not be set to the value except for “1010” and “0101”.
Default: “1010”
The write operation to TMASTER bit is enabled when TE3-0 bits = “0101”.
0: Except EXT Master Mode (default)
1: EXT Master Mode
Register Name
ALC Mode Control 2
Register Name
Mode Control 1
Register Name
Mode Control 2
In TDM mode at master operation, LRCK can be output by writing “1” at TMASTER bit.
Default
Default
Default
ALCA
D7
TE3
D7
0
D7
1
0
0
ZELMNA
TE2
D6
D6
0
0
D6
0
0
LMATA1
- 58 -
TE1
D5
D5
0
1
D5
0
0
LMATA0
TE0
D4
D4
0
0
D4
0
0
RGA1
D3
D3
0
D3
0
0
0
0
RGA0
D2
D2
D2
0
0
0
0
0
LMTHA1
TMASTER
LFST
D1
D1
0
0
D1
0
[AK5702]
LMTHA0
2007/06
ALC4
D0
D0
0
D0
0
0
0