AK5702VN AKM [Asahi Kasei Microsystems], AK5702VN Datasheet - Page 30
AK5702VN
Manufacturer Part Number
AK5702VN
Description
4-Channel ADC with PLL & MIC-AMP
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet
1.AK5702VN.pdf
(76 pages)
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DIF1
In DSP mode 0, the audio I/F timing is changed by BCKP and MSBS bits.
When BCKP bit is “0”, SDTO data is output by rising edge (“↑”) of BCLK/BCLK.
When BCKP bit is “1”, SDTO data is output by falling edge (“↓”) of BCLK/BCLK.
MSB data position of SDTO can be shifted by MSBS bit. The shifted period is a half of BCLK/BCLK.
If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1”
at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data
and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit
data.
MS0623-E-00
0
DIF0
0
MSBS
0
0
1
1
BCKP
0
1
0
1
MSB of SDTO is output by the rising edge (“↑”) of the first
BCLK after the rising edge (“↑”) of LRCK.
MSB of SDTO is output by the falling edge (“↓”) of the first
BCLK after the rising edge (“↑”) of LRCK.
MSB of SDTO is output by next rising edge (“↑”) of the falling
edge (“↓”) of the first BCLK after the rising edge (“↑”) of
LRCK.
MSB of SDTO is output by next falling edge (“↓”) of the rising
edge (“↑”) of the first BCLK after the rising edge (“↑”) of
LRCK.
Table 17. Audio Interface Format in Mode 0
Audio Interface Format
- 30 -
Figure 25
Figure 26
Figure 27
Figure 28
Figure
[AK5702]
2007/06
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