ISPPAC-CLK5510V LATTICE [Lattice Semiconductor], ISPPAC-CLK5510V Datasheet - Page 15

• Manufacturer Part Number: ISPPAC-CLK5510V
• Description: In-System Programmable Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
match. The option of which mode to use is programmable and may be set using PAC-Designer software (available
from Lattice’s web site at www.latticesemi.com).
In phase-lock mode the lock detector asserts the LOCK signal as soon as a lock condition is determined. In fre-
quency-lock mode, however, the PLL must be in a locked condition for a set number of phase detector cycles
before the LOCK signal will be asserted. The number of cycles required before asserting the LOCK signal in fre-
quency-lock mode can be set from 16 through 256, in increments of 16.
When the lock condition is lost the LOCK signal will be de-asserted immediately both in phase and frequency-lock
modes.
Loop Filter
A simplified schematic for the ispClock5500 loop filter is shown in Figure 11. The filter’s capacitors are fixed, and
the response is controlled by setting the value of the phase-detector’s output current source’s and the value of the
variable resistor. The phase detector output current has 14 possible settings, ranging from 3µA to 55µA, while the
resistor may be set to any one of six values ranging from 2.3K to 9.3K. This provides a total of 84 unique I-R com-
binations which may be selected.
Figure 11. ispClock5500 Loop Filter (Simplified)
Because the selection of an optimal PLL loop filter can be a daunting task, PAC-Designer software offers a set of
default filter settings which will provide acceptable performance for most applications. The primary criterion for
selecting one of these settings is the total division factor used in the feedback path, or the ratio between the VCO
output frequency and the frequency output by the N feedback divider (N x V
tings and conditions under which they should be used.
Table 2. PAC-Designer Recommended Loop Filter Settings
M-divider
N-divider
From
From
N x V
12 to 14
18 to 20
24 to 26
32 to 64
2 to 8
Phase Detector
10
16
22
28
30
FBK
I
I
I (µA)
15
11
13
15
17
19
21
22
5
7
9
C
1
R (kΩ)
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
ispClock5500 Family Data Sheet
feedback
R
C
2
). Table 2 lists these default set-
To VCO