ISPPAC-CLK5510V LATTICE [Lattice Semiconductor], ISPPAC-CLK5510V Datasheet - Page 22

• Manufacturer Part Number: ISPPAC-CLK5510V
• Description: In-System Programmable Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Each of the ispClock5500’s output driver banks can be configured to support the following logic outputs:
To provide LVTTL, LVCMOS, SSTL2, SSTL3, and HSTL outputs, the CMOS output drivers in each bank are
enabled. These circuits provide logic outputs which swing from ground to the VCCO supply rail. The choice of
VCCO to be supplied to a given bank is determined by the logic standard to which that bank is configured. Because
each pair of outputs has its own VCCO supply pin, each bank can be independently configured to support a differ-
ent logic standard. Note that the two outputs associated with a bank must necessarily be configured to the same
logic standard. The source impedance of each of the two outputs in each bank may be independently set over a
range of 40Ω to 70Ω in 5Ω steps. A low impedance option (≈20Ω) is also provided for cases where low source ter-
mination is desired on a given output, such as when using HSTL output mode.
Control of output slew rate is also provided in LVTTL, LVCMOS, SSTL2, SSTL3, and HSTL output modes. Four
output slew-rate settings are provided, as specified in the “Output Rise Times” and “Output Fall Times” tables in this
data sheet.
To provide LVDS and differential LVPECL outputs, a separate driver is used which provides the correct LVDS or
LVPECL logic levels when operating from a 3.3V VCCO. Because both LVDS and differential LVPECL transmission
lines are normally terminated with a single 100Ω resistor between the ‘+’ and ‘-’ signal lines at the far end, the
ispClock5500’s internal termination resistors are not available in these modes. Also note that output slew-rate con-
trol is not available in LVDS or LVPECL mode, and that these drivers always operate at a fixed slew-rate.
Polarity control (true/inverted) is available for all output drivers. In the case of single-ended output standards, the
polarity of each of the two output signals from each bank may be controlled independently. In the case of differen-
tial output standards, the polarity of the differential pair may be selected.
Suggested Usage
Figure 19 shows a typical configuration for the ispClock5500’s output driver when configured to drive an LVTTL or
LVCMOS load. The ispClock5500’s output impedance should be set to match the characteristic impedance of the
transmission line being driven. The far end of the transmission line should be left open, with no termination resis-
tors.
Figure 19. Configuration for LVTTL/LVCMOS Output Modes
Figure 20 shows a typical configuration for the ispClock5500’s output driver when configured to drive SSTL2,
SSTL3, or HSTL loads. The ispClock5500’s output impedance should be set to 40Ω for driving SSTL2 or SSTL3
• LVTTL
• LVCMOS (1.8V, 2.5V, 3.3V)
• SSTL2
• SSTL3
• HSTL
• LVDS
• Differential LVPECL (3.3V)
LVCMOS/LVTTL
Mode
ispClock5500
Ro = Zo
22
Zo
ispClock5500 Family Data Sheet
LVCMOS/LVTTL
Receiver