ISPPAC-CLK5510V LATTICE [Lattice Semiconductor], ISPPAC-CLK5510V Datasheet - Page 17

• Manufacturer Part Number: ISPPAC-CLK5510V
• Description: In-System Programmable Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Table 3. Nominal Output Duty Cycle vs. V Divider Setting
PLL_BYPASS Mode
The PLL_BYPASS mode is provided so that input reference signals can be coupled through to the outputs without
using the PLL functions. When PLL_BYPASS mode is enabled (PLL_BYPASS=HIGH), the output of the M divider
is routed directly to the inputs of the V dividers. In PLL_BYPASS mode, the nominal values of the V dividers are
halved, so that they provide division ratios ranging from 1 to 32. The divide-by-1 setting, however, is invalid and will
produce undefined results. The output frequency for a given V divider (f
Please note that PLL_BYPASS mode is provided primarily for testing purposes. When PLL_BYPASS mode is
enabled, features such as lock detect and skew generation are unavailable.
Reference Inputs
The ispClock5500 provides sets of configurable, internally-terminated inputs for clock reference signals. In normal
operation, the clock reference input (REFA) is connected to the system clock from which the output signals are to
be derived.
The ispClock5510 provides one input signal pair for reference input, while the ispClock5520 provides two input
pairs for reference signals. To select between reference inputs, the ispClock5520 provides a CMOS-compatible dig-
ital input called REFSEL. Table 4 shows the behavior of this control input:
Table 4. REFSEL Operation for ispClock5520
Clock reference inputs may be configured to interface to signals from the following logic families with little or no
external support circuitry:
Each input also features internal programmable termination resistors, as shown in Figure 12.
• LVTTL (3.3V)
• LVCMOS (1.8V, 2.5V, 3.3V)
• SSTL2
• SSTL3
• HSTL
• LVDS
• LVPECL (differential, 3.3V)
10
12
14
16
V
2
4
6
8
DC%
50
50
67
50
40
50
43
50
18
20
22
24
26
28
30
32
V
REFSEL
0
1
DC%
44
50
45
50
46
50
47
50
f
k
=
Selected Input Pair
17
M x V
f
ref
REFB+/-
REFA+/-
k
34
36
38
40
42
44
46
48
V
k
) will be determined by
ispClock5500 Family Data Sheet
DC%
47
50
47
50
48
50
48
50
50
52
54
56
58
60
62
64
V
DC%
48
50
48
50
48
50
48
50
(2)